82374EB Datasheet, PDF (42/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Pin Name
Description
4
IDE DECODE Bit 4 is used to enable or disable IDE locations 1F0h – 1F7h (primary) or 170h –
177h (secondary) and 3F6h 3F7h (primary) or 376h 377h (secondary)
82374EB
When this bit is set to 0 the IDE encoded chip select signals and the X-Bus transceiver signal
(XBUSOE ) are not generated for these addresses
82374SB
When this bit is set to 0 the IDE encoded chip select signals and the X-Bus transceiver signal
(XBUSOE ) are not generated for addresses 1F0h – 1F7h (primary) or 170h – 177h (secondary)
and 3F6h or 376h Note that read write accesses to addresses 377h and 3F7h are not
disabled and still generate XBUSOE
1
KEYBOARD CONTROLLER DECODE Enables (1) or disables (0) the keyboard controller
address locations 60h (82374EB SB) 62h (82374EB only) 64h (82374EB SB) and 66h
(82374EB only) When this bit is set to 0 the keyboard controller encoded chip select signals
and the X-Bus transceiver signal (XBUSOE ) are not generated for these locations Note that
the value of this bit affects control function (keyboard controlling mapping) provided by bit 6 of
this register
0
Bit 0 REAL TIME CLOCK DECODE Enables (1) or disables (0) the RTC address locations
70h–77h When this bit is set to 0 the RTC encoded chip select signals RTCALE RTCRD
RTCWR and XBUSOE signals are not generated for these addresses
3 1 8 PCSB PERIPHERAL CHIP SELECT B REGISTER
Address Offset
Default Value
Attribute
Size
4Fh
CFh
Read Write
8 Bits
This register is used to enable or disable generation of the X-Bus transceiver signal (XBUSOE ) for accesses
to the serial ports and parallel port locations When disabled the XBUSOE signal for that device will not be
generated
Bit
Description
7 CRAM Decode This bit is used to enable (1) or disable (0) I O write accesses to location 0C00h and
I O read write accesses to locations 0800h – 08FFh The configuration RAM read and write
(CRAMRD CRAMWR ) strobes are valid for accesses to 0800h – 08FFh
6 Port 92 Decode This bit is used to disable (0) access to Port 92 This bit defaults to enable (1) at
PCIRST
5 4 Parallel Port Decode These bits are used to select which Parallel Port address range (LPT1 2 or 3)
is decoded
Bits 5 4
00
01
10
11
Decode
LPT1 (3BCh–3BFh)
LPT2 (378h–37Fh)
LPT3 (278h–27Fh)
Disabled
42