82374EB Datasheet, PDF (144/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
7 1 Arbitration Priority
At the top level of the arbiter the ESC uses a three way rotating priority arbitration method On a fully loaded
bus the order in which the devices are granted bus access is independent of the order in which they assert a
bus request since devices are serviced based on their position in the rotation The arbitration scheme assures
that DMA channels and EISA masters are able to access the bus with minimal latency
The PCEB and EISA Masters share one of the slots in the three way rotating priority scheme This sharing is a
two way rotation between the CPU and EISA Masters as a group In this arbitration scheme the PCEB acts on
behalf of the CPU and all other PCI masters
EISA Masters have a rotating priority structure which can handle up to eight master requests
The next position in the top level arbiter is occupied by the DMA The DMA’s DREQ lines can be placed in
either fixed or rotating priority The default mode is fixed and by programming the DMA Command registers
the priority can be modified to rotating priority mode
7 2 Preemption
An EISA compatible arbiter ensures that minimum latencies are observed for both EISA DMA devices and
EISA Masters
7 2 1 PCEB EISA BUS ACQUISITION AND PCEB PREEMPTION
EISA bus arbitration is intended to be optimized for CPU access the EISA bus Since the CPU accesses to the
EISA Bus through the PCEB the PCEB is assumed to be the default owner of the EISA bus The arbitration
interface between the PCEB and the ESC is implemented as a HOLD HLDA (EISAHOLD EISAHLDA) pair
If a PCI cycle requires access to the EISA Bus while EISAHLDA signal is asserted (EISA Bus busy) the PCI
cycle is retried and the PCEB requests the EISA bus by asserting PEREQ The ESC after sampling PER-
EQ asserted preempts the current owner of the EISA Bus The ESC grants the EISA Bus by negating
EISAHOLD signal
The ESC asserts EISAHOLD to the PCEB when the ESC needs to acquire the ownership of the EISA bus
While EISAHOLD is asserted the arbitration process is dynamic and may change (i e the ESC is still accept-
ing EISA Bus requests) When the PCEB returns EISAHLDA the arbiter freezes the arbitration process and
determine the winner If the new winner is an EISA Master or DMA channel the ESC will assert NMFLUSH
The ESC tri-states the NMFLUSH output driver on the following clock The PCEB holds NMFLUSH assert-
ed until all buffers are flushed After all buffers are flushed the PCEB negates NMFLUSH and then tri-state
the output buffer After sampling NMFLUSH negated the ESC resumes driving NMFLUSH on the next PCI
clock This way the ESC does not assert MACK or DACK until the PCEB acknowledges that all line buffers
have been flushed
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