82374EB Datasheet, PDF (59/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Bit
Description
7 3 Reserved Must be 0
2 DMA Channel Mask Set Clear Writing a 1 to bit 2 sets the mask bit and disables the incoming DREQ
for the selected channel Writing a 0 to bit 2 clears the mask bit and enables the incoming DREQ for
the elected channel
1 0 DMA Channel Select Bits 1 0 select the DMA Channel Mode Register to program with bit 2
Bits 1 0
00
01
10
11
Channel
Channel 0 (4)
Channel 1 (5)
Channel 2 (6)
Channel 3 (7)
3 2 6 WAMB WRITE ALL MASK BITS REGISTER
Register Location
Default Value
Attribute
Size
0Fh Channels 0-3
0DEh Channels 4-7
0Fh
Read Write
8 Bits
This command allows enabling and disabling of incoming DREQ assertions by writing the mask bits for each
controller DMA1 or DMA2 simultaneously rather than by individual channel as is done with the ‘‘Write Single
Mask Bit’’ command Two registers store the current mask status for DMA1 and DMA2 Setting the mask bit
disables the incoming DREQ x for that channel Clearing the mask bit enables the incoming DREQ x Unlike
the ‘‘Write Single Mask Bit’’ command this command includes a status read to check the current mask status
of the selected DMA channel group When read the mask register current status appears on bits 3 0 A
channel’s mask bit is automatically set when the Current Word Count register reaches terminal count (unless
the channel is programmed for autoinitialization) The entire register is also set by a reset or a Master Clear
Setting the entire register disables all DMA requests until a clear Mask register instruction allows them to
occur
Two important points should be taken into consideration when programming the mask registers First individu-
ally masking DMA Channel 4 (DMA controller 2 Channel 0) will automatically mask DMA Channels 3 0 as
this channel group is logically cascaded onto Channel 4 Second masking off DMA controller 2 with a write to
port 0DEh will also mask off DREQ assertions from DMA controller 1 for the same reason when DMA Channel
4 is masked so are DMA Channels 0-3
59