82374EB Datasheet, PDF (130/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
The DMA Controller is at any time either in master mode or slave mode In master mode the DMA controller is
either servicing a DMA slave’s request for DMA cycles allowing an ISA master to use the bus via a cascaded
DREQ signal or granting the bus to an EISA master via MREQ MACK In slave mode the ESC monitors
both the EISA bus decoding and responding to I O read and write commands that address its registers
When the DMA is in master mode and servicing a DMA slave it works in conjunction with the ESC EISA bus
controller to create bus cycles on the EISA bus The DMA places addresses onto the internal address bus and
the bus controller informs the DMA when to place a new address on the internal bus
6 2 DMA Transfer Modes
The channels can be programmed for any of four transfer modes The transfer modes include single block
demand or cascade Each of the three active transfer modes (single block and demand) can perform three
different types of transfers (read write or verify) The ESC does not support memory to memory transfers
6 2 1 SINGLE TRANSFER MODE
In Single Transfer mode the DMA is programmed to make one transfer only The byte word count will be
decremented and the address decremented or incremented following each transfer When the byte word
count ‘‘rolls over’’ from zero to FFFFFFh or an external EOP is encountered a Terminal Count (TC) will load a
new buffer via Scatter-Gather buffer chaining or autoinitialize if it is programmed to do so
DREQ must be held active until DACK becomes active in order to be recognized If DREQ is held active
throughout the single transfer the bus will be released to the CPU after a single transfer With the DREQ
asserted high the DMA I O device will rearbitrate for the bus Upon winning the bus another single transfer
will be performed This allows other bus masters a chance to arbitrate for win and execute cycles on the EISA
Bus
6 2 2 BLOCK TRANSFER MODE
In Block Transfer mode the DMA is activated by DREQ to continue making transfers during the service until a
TC caused by either a byte word count going to FFFFFFh or an external EOP is encountered DREQ need
only be held active until DACK becomes active If the channel has been programmed for it a new buffer will be
loaded by buffer chaining or auto-initialization at the end of the service In this mode it is possible to lock out
other devices for a period of time (including refresh) if the transfer count is programmed to a large number and
Compatible timing is selected Block mode can effectively be used with Type ‘‘A’’ Type ‘‘B’’ or Burst timing
since the channel can be interrupted through the 4 ms timeout mechanism and other devices (or Refresh) can
arbitrate for and win the bus See Section 7 0 on the EISA Bus Arbitration for a detailed description of the 4 ms
timeout mechanism Note that scatter-gather block mode is not supported
6 2 3 DEMAND TRANSFER MODE
In Demand Transfer mode the DMA channel is programmed to continue making transfers until a TC (Terminal
Count) is encountered or an external EOP is encountered or until the DMA I O device pulls DREQ inactive
Thus transfers may continue until the I O device has exhausted its data capacity After the I O device catches
up the DMA service is re-established when the DMA I O device reasserts the channel’s DREQ During the
time between services when the system is allowed to operate the intermediate values of address and byte
word count are stored in the DMA controller Current Address and Current Byte Word Count registers A TC
can cause a new buffer to be loaded via Scatter-Gather buffer chaining or autoinitialize at the end of the
service if the channel has been programmed for it
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