82374EB Datasheet, PDF (54/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
3 2 2 DCM DMA CHANNEL MODE REGISTER
Register Location
Default Value
Attribute
Size
0Bh Channels 0-3
0D6h Channels 4-7
000000xxb
Write Only
8 Bits
Each channel has a Mode Register associated with it The Mode registers provide control over DMA Transfer
type transfer mode address increment decrement and autoinitialization When writing to the register
bits 1 0 determine which channel’s Mode Register will be written and are not stored Only bits 7 2 are stored
in the mode register This register is set to the default value upon reset and Master Clear Its default value is
Verify transfer autoinitialize disable Address increment and Demand mode Channel 4 defaults to cascade
mode and cannot be programmed for any mode other than cascade mode
Bit
Description
7 6 DMA Transfer Mode Each DMA channel can be programmed in one of four different modes single
transfer block transfer demand transfer and cascade
Bits 7 6
00
01
10
11
Transfer Mode
Demand mode
Single mode
Block mode
Cascade mode
5 Address Increment Decrement Select Bit 5 controls address increment decrement during multi-
byte DMA transfers When bit 5^e0 address increment is selected When bit 5^e1 address decrement
is selected Address increment is the default after a PCIRST cycle or Master Clear command
4 Autoinitialize Enable When bit 4^e1 the DMA restores the Base Page Address and Word count
information to their respective current registers following a terminal count (TC) When bit 4^e0 the
autoinitialize feature is disabled and the DMA does not restore the above mentioned registers A
PCIRST or Master Clear disables autoinitialization (sets bit 4 to 0)
3 2 DMA Transfer Type Verify write and read transfer types are available Verify transfer is the default
transfer type upon PCIRST or Master Clear Write transfers move data from an I O device to
memory Read transfers move data from memory to an I O device Verify transfers are pseudo
transfers addresses are generated as in a normal read or write transfer and the device responds to
EOP etc However with Verify transfers the ISA memory and I O cycle lines are not driven Bit
combination 11 is illegal When the channel is programmed for cascade ( 7 6 ^e11) the transfer type
bits are irrelevant
Bits 3 2
00
01
10
11
Transfer Type
Verify transfer
Write transfer
Read Transfer
Illegal
1 0 DMA Channel Select Bits 1 0 select the DMA Channel Mode Register that will be written by
bits 7 2
Bits 1 0
00
01
10
11
Channel
Channel 0 (4)
Channel 1 (5)
Channel 2 (6)
Channel 3 (7)
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