82374EB Datasheet, PDF (25/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
2 5 EISA Arbitration Signals
Pin Name
MREQ 3 0
MREQ 7 4
PIRQ 0 3
Type
Description
in MASTER REQUEST MREQ 3 0 are slot specific signals used by EISA bus
masters to request bus access MREQ once asserted must remain asserted
until the corresponding MACK is asserted The MREQ is negated on the falling
edge of BCLK slightly before the end of a master transfer The LA BE
M IO and W R lines should be floated on or before the rising edge of BCLK
after MREQ is negated The end of the last bus cycle is derived from CMD in
this case The MREQ signals are asserted on the falling edge of BCLK MREQ
is always sampled on the rising edge of BCLK MREQ is synchronous with
respect to BCLK After asserting MREQ the corresponding master must not
assert MREQ until 1 5 BCLKs after CMD is negated
in MASTER REQUEST PCI INTERRUPT REQUEST These pins behave in one of
two modes depending on the state of the Mode Select Register bit 1 and bit 0
Master Request MREQ lines are slot specific signals used by EISA bus masters
to request bus access This signal behave in the same manner as MREQ 3 0
signals
PCI Interrupt Request PIRQ are used to generate asynchronous interrupts to
the CPU via the Programmable Interrupt Controller (82C59) integrated in the ESC
These signals are defined as level sensitive and are asserted low The PIRQx
can be shared with PC compatible interrupts IRQ3 IRQ7 IRQ9 IRQ15 The
PIRQx Route Control Register determines which PCI interrupt is shared with
which PC compatible interrupt
Register
Bit 1 0
00
01
10
11
MREQ7
PIRQ0
PIRQ0
PIRQ0
PIRQ0
MREQ7
Pins
MREQ6 MREQ5
PIRQ1
PIRQ2
PIRQ1
PIRQ2
PIRQ1
MREQ5
MREQ6 MREQ5
MREQ6 MREQ5
MREQ4
PIRQ3
PIRQ3
MREQ4
MREQ4
MREQ4
25