82374EB Datasheet, PDF (75/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
If a counter is programmed to read write two-byte counts the following precaution applies A program must
not transfer control between writing the first and second byte to another routine which also writes into that
same counter Otherwise the counter will be loaded with an incorrect count The count must always be
completely loaded with both bytes
Bits 6 and 7 are also used to select the counter for the control word you are writing
Following reset the control words for each register are undefined You must program each timer to bring it into
a known state However each counter OUT signal is reset to 0 following reset The SPKR output interrupt
controller input IRQ0 (internal) bit 5 of port 061h and the internally generated Refresh request are each reset
to 0 following reset
Bit
Description
7 6 Counter Select The Counter Selection bits select the counter the control word acts upon as shown
below The Read Back Command is selected when bits 7 6 are both 1
Bit 7 6
00
01
10
11
Function
Counter 0 select
Counter 1 select
Counter 2 select
Read Back Command (see Section 3 3 2)
5 4 Read Write Select Bits 5 4 are the read write control bits The Counter Latch Command is selected
when bits 5 4 are both 0 The read write options include read write least significant byte read write
most significant byte or read write the LSB and then the MSB The actual counter programming is
done through the counter I O port (040h 041h and 042h for counters 0 1 and 2 respectively)
Bit 5 4
00
01
10
11
Function
Counter Latch Command (see Section 3 3 3)
R W Least Significant Byte (LSB)
R W Most Significant Byte (MSB)
R W LSB then MSB
3 1 Counter Mode Selection Bits 3 1 select one of six possible modes of operation for the counter as
shown below Note that for the fail safe timer (timer 2 counter 0) modes 1 2 3 4 and 5 are reserved
Bit 3 1
000
001
X10
X11
100
101
Mode
0
1
2
3
4
5
Function
Out signal on end of count (^e0)
Hardware retriggerable one-shot (Reserved for timer 2 counter 0 )
Rate generator (divide by n counter) (Reserved for timer 2 counter 0 )
Square wave output (Reserved for timer 2 counter 0 )
Software triggered strobe (Reserved for timer 2 counter 0 )
Hardware triggered strobe (Reserved for timer 2 counter 0 )
0 Binary BCD Countdown Select When bit 0^e0 a binary countdown is used The largest possible
binary count is 2¹⁶ When bit 0^e1 a binary coded decimal (BCD) count is used The largest BCD
count allowed is 104
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