82374EB Datasheet, PDF (125/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
5 6 Data Swap Buffer Control Logic
For all mis-matched cycles the ESC is responsible for performing data size translations The ESC performs
these data size translations by either becoming the master of the EISA ISA Bus (see Section 5 3 4) or by
directing the flow of data to the appropriate byte lanes In both cases the ESC generates Data Swap Buffer
control signals to perform data size translation
 SDCPYEN 13 3 1
 SDCPYUP
 SDOE 2 0
 SDLE 3 0
The Data Swap Buffers are integrated in the PCEB (see PCEB data sheet Section 8 0 for Data Swap Buffer
function description) The data size translation cycles consist of one or combinations of Assembly Disassem-
bly Copy Up Down and Redrive
ASSEMBLY
This occurs during reads when an EISA master data size is greater than the slave data size ISA masters are
required to perform assemble when accessing 8-bit slaves Assembly consists of two three or four cycles
depending on the master data size slave data size and number of active byte enables During the assembly
process the data is latched in to the PCEB data latch buffers This data is driven or redriven on to the EISA
bus during the last cycle The master after initiating the cycle backs-off the bus (see the EISA master back-off
section for details) when a mis-matched is detected The ESC becomes the bus master and runs the appropri-
ate number of cycles At the end of the last cycle the ESC transfer the control of bus back to the original
master
DISASSEMBLY
This occurs during writes when the EISA master data size is greater than the slave data size ISA masters are
required to perform disassemble when accessing 8-bit slaves Disassembly consists of two three or four
cycles depending on the master data size slave data size and number of active byte enables During the
disassembly process the data is latched in the PCEB latch buffers on the first cycle This data is driven or
redriven on to the EISA bus on subsequent cycles The master after initiating the cycle backs-off the bus (see
the EISA master back-off section for details) when a mis-matched is detected The ESC becomes the bus
master and runs the appropriate number of cycles At the end of the last cycle the ESC transfer the control of
bus back to the original master
COPY-UP
This occurs during reads when the master data size is greater than the slave data size and during writes when
the master data size is smaller than the slave data size The copy-up function is used for cycles with and
without assembly disassembly
COPY-DOWN
This occurs during writes when the master data size is greater than the slave data size and during reads when
the master data size is smaller than the slave data size The copy-down function is used for cycles with and
without assembly disassembly
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