82374EB Datasheet, PDF (60/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Bit
Description
7 4 Reserved Must be 0
3 0 Channel Mask Bits Setting the bit(s) to a 1 disables the corresponding DREQ(s) Setting the bit(s) to
a 0 enables the corresponding DREQ(s) Bits 3 0 are set to 1 upon PCIRST or Master Clear When
read bits 3 0 indicate the DMA channel 3 0 ( 7 4 ) mask status
Bit Channel
0
0(4)
1
1(5)
2
2(6)
3
3(7)
NOTE
Disabling channel 4 also disables channels 0-3 due to the cascade of DMA1 through channel 4
of DMA2
3 2 7 DS DMA STATUS REGISTER
Register Location
Default Value
Attribute
Size
08h Channels 0-3
0D0h Channels 4-7
00h
Read Only
8 Bits
Each DMA controller has a read-only Status register A Status register read is used when determining which
channels have reached terminal count and which channels have a pending DMA request Bits 3 0 are set
every time a TC is reached by that channel These bits are cleared upon reset and on each Status Read
Bits 7 4 are set whenever their corresponding channel is requesting service
Bit
Description
7 4 Request Status When a valid DMA request is pending for a channel (on its DREQ signal line) the
corresponding bit is set to 1 When a DMA request is not pending for a particular channel the
corresponding bit is set to 0 The source of the DREQ may be hardware a timed-out block transfer or
a software request Note that channel 4 does not have DREQ or DACK lines so the response for a
read of DMA2 status for channel 4 is irrelevant
Bit Channel
4
0
5
1(5)
6
2(6)
7
3(7)
3 0 Terminal Count Status When a channel reaches terminal count (TC) its status bit is set to 1 If TC
has not been reached the status bit is set to 0 Note that channel 4 is programmed for cascade and is
not used for a DMA transfer Therefore the TC bit response for a status read on DMA2 for channel 4 is
irrelevant
Bit Channel
0
0
1
1(5)
2
2(6)
3
3(7)
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