82374EB Datasheet, PDF (48/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Pin Name
Description
2
STPCLK Scaling Enable (CSTPCLKSC) This bit enables disables control of the STPCLK
high low times by the clock scaling timers When bit 2^e1 the STPCLK signal scaling control
is enabled When enabled (and bit 1^e1 enabling the STPCLK signal) the high and low times
for the STPCLK signal are controlled by the Clock Scaling STPCLK High Timer and Clock
Scaling STPCLK Low Timer Registers respectively When bit 2^e0 (default) the scaling
control of the STPCLK signal is disabled
1
STPCLK Signal Enable (CSTPCLKE) This bit permits software to place the CPU into a low
power state When bit 1^e1 the STPCLK signal is enabled and a read from the APMC
Register causes STPCLK to be asserted When bit 1^e0 (default) the STPCLK signal is
disabled and is negated (high) Software can set this bit to 0 by writing a 0 to it or by any write to
the APMC Register
0
SMI Gate (CSMIGATE) When bit 0^e1 the SMI signal is enabled and a system
management interrupt condition causes the SMI signal to be asserted When bit 0^e0
(default) the SMI signal is masked and negated This bit only affects the SMI signal and
does not effect the detection recording of SMI events (i e This bit does not effect the SMI
status bits in the SMIREQ Register) Thus SMI conditions can be pending when this bit is set to
1 If an SMI is pending when this bit is set to 1 the SMI signal is asserted
3 1 20 SMIEN SMI ENABLE REGISTER
Address Offset
Default Value
Attribute
Size
A2-A3h
0000h
Read Write
16 Bits
For the 82374SB his register enables the generation of SMI (asserting the SMI signal) for the associated
hardware events (bits 5 0 ) and software events (bit 7) When a hardware event is enabled the occurrence of
a corresponding event results in the assertion of SMI if enabled via the SMICNTL Register The SMI is
asserted independent of the current power state (Power-On or Fast Off) The default for all sources in this
register is disabled
Bit
Description
15 8 Reserved
7 APMC Write SMI Enable This bit enables SMI for writes to the APMC Register When bit 7^e1
writes to the APMC Register generate an SMI When bit 7^e0 writes to the APMC Register do not
generate an SMI
6 EXTSMI SMI Enable When bit 6^e1 asserting the EXTSMI input signal generates an SMI When
bit 6^e0 asserting EXTSMI does not generate an SMI
5 Fast Off Timer SMI Enable This bit enables the Fast Off Timer to generate an SMI When bit 5^e1
the timer generates an SMI when it decrements to zero When bit 5^e0 the timer does not generate
an SMI
4 IRQ12 SMI Enable (PS 2 Mouse Interrupt) This bit enables the IRQ12 signal to generate an SMI
When bit 4^e1 asserting the IRQ12 input signal generates an SMI When bit 4^e0 asserting IRQ12
does not generate an SMI
3 IRQ8 SMI Enable (RTC Alarm Interrupt) This bit enables the IRQ8 signal to generate an SMI
When bit 3^e1 asserting the IRQ8 input signal generates an SMI When bit 3^e0 asserting IRQ8
does not generate an SMI
48