82374EB Datasheet, PDF (141/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
6 7 6 AUTOINITIALIZE
By programming a bit in the Mode register a channel may be set up as an autoinitialize channel During
Autoinitialization the original values of the Current page Current address and Current Byte Word Count
registers are automatically restored from the Base Address and Word count registers of that channel following
TC The Base registers are loaded simultaneously with the Current registers by the microprocessor and remain
unchanged throughout the DMA service The mask bit is not set when the channel is in autoinitialize Following
autoinitialize the channel is ready to perform another DMA service without CPU intervention as soon as a
valid DREQ is detected (Note Autoinitialize will not function if the channel is also programmed for Scatter-
Gather or buffer chaining Only one of these features should be enabled at a time )
6 8 Software Commands
These are additional special software commands which can be executed in the Program Condition They do
not depend on any specific bit pattern on the data bus The three software commands are
1 Clear Byte Pointer Flip-Flop
2 Master Clear
3 Clear Mask Register
6 8 1 CLEAR BYTE POINTER FLIP-FLOP
This command is executed prior to writing or reading new address or word count information to the DMA This
initializes the flip-flop to a known state so that subsequent accesses to register contents by the microproces-
sor will address upper and lower bytes in the correct sequence
When the CPU is reading or writing DMA registers two Byte Pointer Flip-Flops are used one for Channels 0-3
and one for Channels 4-6 Both of these act independently There are separate software commands for
clearing each of them (0Ch for Channels 0-3 0D8h for Channels 4-7)
An additional Byte Pointer Flip-Flop has been added for use when EISA masters are reading and writing DMA
registers (The arbiter state will be used to determine the current master of the bus ) This Flip-Flop is cleared
when an EISA Master performs a write to either 00Ch or 0D8h there is one Byte Pointer Flip Flop per eight
DMA channels This Byte Pointer was added to eliminate the problem of the CPU’s byte pointer getting out of
synchronization if an EISA Master takes the bus during the CPU’s DMA programming
6 8 2 DMA MASTER CLEAR
This software instruction has the same effect as the hardware Reset The Command Status Request and
Internal First Last Flip-Flop registers are cleared and the Mask register is set The DMA Controller will enter
the idle cycle
There are two independent Master Clear Commands 0Dh which acts on Channels 0-3 and 0DAh which acts
on Channels 4-6
6 8 3 CLEAR MASK REGISTER
This command clears the mask bits of all four channels enabling them to accept DMA requests I O port 00Eh
is used for Channels 0-3 and I O port 0DCh is used for Channels 4-6
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