82374EB Datasheet, PDF (190/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Software can assert STPCLK if enabled via the SMICNTL Register by a read of the APMC Register Note
that STPCLK can also be periodically asserted by using clock scaling as described below
The ESC automatically negates STPCLK when a break event occurs (if enabled in the SEE Register) and the
CPU stop grant special cycle has been received Software can negate STPCLK by disabling STPCLK in
the SMICNTL Register or by a write to the APMC Register
NOTE
1 INIT is always enabled as a break event Otherwise INIT acts exactly as other break events
If STPCLK is negated when INIT is asserted the STPCLK high timer is reloaded
If INIT is asserted when STPCLK is asserted but before the stop grant bus cycle STPCLK negation
waits until after the stop grant bus cycle This happens after the CPU is reset when it samples STPCLK
still asserted
If INIT is asserted when STPCLK is asserted and after the stop grant bus cycle STPCLK is negated
immediately This guarantees that STPCLK will be negated after the CPU is reset
2 While the STPCLK signal is asserted the external interrupts (NMI SMI and INT) may be asserted to the
CPU If INTR is asserted it will remain asserted until the CPU INTA cycle is detected If SMI (or NMI) is
asserted it remains asserted until the SMI (or NMI) handler clears the ESC’s CSMIGATE (or sets the ESC’s
NMIMASK bit) Thus SMI NMI and INTR can be applied to the CPU independent of the STPCLK signal
state Note that when SMI NMI and IRQx are enabled as break events the occurrence of the break
event negates STPCLK
Clock Scaling (Emulating Clock Division)
Clock scaling permits the ESC to periodically place the CPU in a low power state This emulates clock division
When clock scaling is enabled the CPU runs at full frequency for a pre-defined time period and then is
stopped for a pre-defined time period The run stop time interval ratio emulates the clock division effect from a
power performance point of view However clock scaling is more effective than dividing the CPU frequency
For example if the CPU is in the stop grant state and a break event occurs the CPU clock returns to full
frequency In addition there is no recovery time latency to start the clock
Two programmable 8-bit clock scale timer control registers set the STPCLK high (negate) and low (assert)
times the CTLTMRH and CTLTMRL Registers The timer is clocked by a 32 ms internal clock This allows a
programmable timer interval for both the STPCLK high and low times of 0-8 ms When enabled via the
SMICNTL Register the STPCLK Timer operates as follows
 When STPCLK is negated the timer is loaded with the value in the CTLTMRH Register and starts
counting down When the timer reaches 00h STPCLK is asserted Since the timer is re-loaded with the
contents of the CTLTMRH Register every time STPCLK is negated (for break events or clock throttling)
the STPCLK minimum inactive time is guaranteed
 When STPCLK is asserted the timer is loaded with the value in the CTLTMRL Register The timer does
not begin to count until the Stop Grant Special Cycle is received When the timer reaches 00h STPCLK is
negated Note that a break event also negates STPCLK
NOTE
If STPCLK is negated and a break event occurs the STPCLK Timer is loaded with the value in
the CTLTMRH Register
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