82374EB Datasheet, PDF (79/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
3 3 5 CAPS COUNTER ACCESS PORTS
Register Location
Default Value
Attribute
Size
040h Timer 1 Counter 0
041h Timer 1 Counter 1
042h Timer 1 Counter 2
048h Timer 2 Counter 0
04Ah Timer 2 Counter 2
xxh
Read Write
8 Bits per counter
Each of these I O ports is used for writing count values to the count registers reading the current count value
from the counter by either an I O read after a counter-latch command or after a read-back command and
reading the Status byte following a read-back command
Bit
Description
7 0 Counter Access Each counter I O port address is used to program the 16 bit count register The
order of programming either LSB only MSB only or LSB then MSB is defined with the Counter
Control register at I O port address 043h The counter I O port is also used to read the current count
from the count register and return the status of the counter programming following a read-back
command
3 4 Interrupt Controller Registers
The ESC contains an EISA compatible interrupt controller that incorporates the functionality of two 82C59
interrupt controllers The interrupt registers control the operation of the interrupt controller and can be ac-
cessed from the EISA Bus via I O space This section describes the Interrupt registers The operation of the
Interrupt Controller is described in Chapter 9 0
3 4 1 ICW1 INITIALIZATION COMMAND WORD 1
Register Location
Default Value
Attribute
Size
020h INT CNTRL-1
0A0h INT CNTRL-2
xxh
Write Only
8 Bits per controller
A write to Initialization Command Word One starts the interrupt controller initialization sequence Addresses
020h and 0A0h are referred to as the base addresses of CNTRL-1 and CNTRL-2 respectively
An I O write to the CNTRL-1 or CNTRL-2 base address with bit 4 equal to 1 is interpreted as ICW1 For ESC-
based EISA systems three I O writes to ‘‘base address ^a 1’’ must follow the ICW1 The first write to ‘‘base
address ^a 1’’ performs ICW2 the second write performs ICW3 and the third write performs ICW4
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