82374EB Datasheet, PDF (91/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Bit
Description
7 4 Not Used These bits exist in the 82077 FDC Refer to the 82077 data sheet for further details
3 DMA Enable When this bit is a 1 the assertion of DACK will result in XBUSOE being asserted If
this bit is 0 DACK2 has no effect on XBUSOE This port bit also exists on the 82077 FDC This bit
defaults to disable (0)
2 0 Not Used These bits exist in the 82077 FDC Refer to the 82077 data sheet for further details
3 5 3 PORT 92 REGISTER
Register Location
Default Value
Attribute
Size
92h
00100100b
Read Write
8 Bits
This register is used to support the alternate reset (ALTRST ) alternate A20 (ALTA20) power-on password
protection and fixed disk light function (DLIGHT ) This register is only accessible if bit 6 in the Peripheral
Chip Select Enable B Register is set to 1
Bit
Description
7 6 Fixed Disk Activity Light These bits are used to turn the Fixed Disk Activity Light on and off When
either of these bits are set to a 1 the light is turned on (DLIGHT driven active) To turn the light off
both of these bits must be 0
5 Reserved This bit is reserved and will always return a 1 when read
4 Not Used This bit is not used and will always return a 0 when read
3 Power on Password Protection A 1 on this bit enables power-on password protection by inhibiting
accesses to the RTC memory for RTC addresses (port 70h) from 36h to 3Fh This is accomplished by
not generating RTCRD and RTCWR signals for theses accesses
2 Reserved This bit is reserved and will always return a 1 when read
1 ALTA20 Signal Writing a 0 to this bit causes the ALTA20 signal to be driven low Writing a 1 to this bit
causes the ALTA20 signal to be driven high
0 ALTRST Signal This read write bit provides an alternate system reset function This function
provides an alternate means to reset the system CPU to effect a mode switch from Protected Virtual
Address Mode to the Real Address Mode This provides a faster means of reset than is provided by
the Keyboard controller This bit is set to a 0 by a system reset Writing a 1 to this bit will cause the
ALTRST signal to pulse active (low) for approximately 4 SYSCLK’s Before another ALTRST pulse
can be generated this bit must be written back to a 0
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