82374EB Datasheet, PDF (179/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Signal
SDCPYEN01
SDCPYEN02
SDCPYEN03
SDCPYEN13
Table 35 Byte Copy Operations
Copy Between Byte Lanes
Byte 0 (bits 7 0 ) and Byte 1 (bits 15 8 )
Byte 0 (bits 7 0 ) and Byte 2 (bits 23 16 )
Byte 0 (bits 7 0 ) and Byte 3 (bits 31 24 )
Byte 1 (bits 15 8 ) and Byte 3 (bits 31 24 )
System Data Copy Up (SDCPYUP)
SDCPYUP controls the direction of the byte copy operations When SDCPYUP is asserted (high) active lower
bytes are copied onto the higher bytes The direction is reversed when SDCPYUP is negated (low)
System Data Output Enable (SDOE 2 0 )
These signals enable the output of the data swap buffers onto the EISA Bus (Table 36) SDOE 2 0 are re-
drive signals in case of mis-matched cycles between EISA to EISA EISA to ISA ISA to ISA and the DMA
cycles between the devices on EISA
Table 36 Output Enable Operations
Signal
Byte Lane
SDOE0
Applies to Byte 0 (bits 7 0 )
SDOE1
Applies to Byte 1 (bits 15 8 )
SDOE2
Applies to Byte 2 and Byte 3 (bits 31 16 )
System Data to Internal (PCEB) Data Latch Enables (SDLE 3 0 )
These signals latch the data from the EISA Bus into the data swap latches The data is then either sent to the
PCI Bus via the PCEB or re-driven onto the EISA Bus SDLE 3 0 latch the data from the corresponding
EISA Bus byte lanes during PCI reads from EISA EISA writes to PCI DMA cycles between an EISA device and
the PCEB These signals also latch data during mismatched cycles between EISA to EISA EISA to ISA ISA to
ISA the DMA cycles between the devices on EISA and any cycles that require copying of bytes as opposed
to copying and assembly disassembly
11 5 Interrupt Acknowledge Control
PEREQ INTA (PCI to EISA Request or Interrupt Acknowledge) is a dual function signal and the selected
function depends on the status of EISAHLDA When EISAHLDA is negated this signal is an interrupt acknowl-
edge (INTA ) and supports interrupt processing If interrupt acknowledge is enabled via the PCEB’s PCICON
Register and EISAHOLDA is negated the PCEB asserts PEREQ INTA when a PCI interrupt acknowledge
cycle is being serviced This informs the ESC that the forwarded EISA I O read from location 04h is an
interrupt acknowledge cycle Thus the ESC uses this signal to distinguish between a request for the interrupt
vector and a read of the ESC’s DMA register located at 04h The ESC responds to the read request by placing
the interrupt vector on SD 7 0
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