82374EB Datasheet, PDF (123/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Figure 8 ISA Master to 16-Bit ISA Slave Extended Cycle (4 BCLKs)
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5 4 3 ISA MASTER TO 8-BIT EISA ISA SLAVE
An 8-bit slave does not positively acknowledge it’s selection by asserting any signal The absence of an
asserted EX32 EX16 M16 and IO16 indicate to the ESC that an 8-bit device has been selected The
EISA master is backed-off the bus and the ESC takes over mastership of the EISA ISA bus The ESC will run
8-bit translation cycles on the bus by deriving the EISA control signals and the ISA control signals A slave can
extend the cycles by negating EXRDY or CHRDY signals The ESC (Internal Registers) is accessed as an 8-bit
slave
5 4 4 ISA WAIT STATE GENERATION
There are three sources that can affect the generation of wait states for ISA cycles The first is the default wait
states which determines the standard or default ISA bus cycle in the absence of any response from the slave
The second is cycle extension which is indicated by the slave pulling the CHRDY signal line inactive (low) The
CHRDY is high by default due to a pull-up resistor Thus the cycle will be extended until the CHRDY is
returned to its active high value The third way to change the number of wait states is when the slave asserts
the NOWS signal which makes the cycle shorter than the default or standard cycle
ISA Memory slaves (8- and 16-bits) and ISA I O slaves (only 8-bits) can shorten their default cycles by
asserting the NOWS signal lines A 16-bit I O slave cannot shorten its default cycles When NOWS is
asserted at the same time the CHRDY is negated by the ISA slave device NOWS will be ignored and wait
states will be added (i e CHRDY has precedence over NOWS )
DMA devices (I O) cannot add wait states but memory can Table 10 shows the number of BCLKs for each
cycle type (Memory I O DMA) default wait states added and with NOWS asserted
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