82374EB Datasheet, PDF (164/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Interrupt Request Register (IRR) 8-bit register which contains the status of each interrupt request line Bits
that are clear indicate interrupts that have not requested service The Interrupt Controller clears the IRR’s
highest priority bit during an interrupt acknowledge cycle (Not effected by IMR)
In-Service Register (ISR) 8-bit register indicating the priority levels currently receiving service Bits that are set
indicate interrupts that have been acknowledged and their interrupt service routine started Bits that are
cleared indicate interrupt requests that have not been acknowledged or interrupt request lines that have not
been asserted Only the highest priority interrupt service routine executes at any time The lower priority
interrupt services are suspended while higher priority interrupts are serviced The ISR is updated when an End
of Interrupt Command is issued
Interrupt Mask Register (IMR) 8-bit register indicating which interrupt request lines are masked
The IRR can be read when prior to the I O read cycle a Read Register Command is issued with OCW3
(RR^e1 RIS^e0)
The ISR can be read when prior to the I O read cycle a Read Register Command is issued with OCW3
(RR^e1 RIS^e1)
The interrupt controller retains the ISR IRR status read selection following each write to OCW3 Therefore
there is no need to write an OCW3 before every status read operation as long as the current status read
corresponds to the previously selected register For example if the ISR is selected for status read by an
OCW3 write the ISR can be read over and over again without writing to OCW3 again However to read the
IRR OCW3 will have to be reprogrammed for this status read prior to the OCW3 read to check the IRR This is
not true when poll mode is used Polling Mode overrides status read when P^e1 RR^e1 in OCW3
After initialization the Interrupt Controller is set to read the IRR
As stated OCW1 is used for reading the IMR The output data bus will contain the IMR status whenever I O
read is active The address is 021h or 061h (OCW1)
9 10 Non-Maskable Interrupt (NMI)
An NMI is an interrupt requiring immediate attention and has priority over the normal interrupt lines (IRQx) The
ESC indicates error conditions by generating a non-maskable interrupt
The ESC generates NMI interrupts based on the following Hardware and Software events
Hardware Events
1 Motherboard Parity Errors Memory parity errors for the motherboard memory These errors are reported
to the ESC through the PERR signal line
2 System Errors System error on the motherboard The system board uses the SERR signal to indicate
system errors to the ESC
3 Add-In Board Parity Errors Parity errors on the add-in memory boards on the EISA expansion bus
IOCHK signal on the EISA bus is driven low by the add-in board logic when this error occurs
4 Fail-Safe Timer Timeout Fail-Safe Timer (Timer 2 Counter 0) count expires If this counter has been set
and enabled and the count expires before a software routine can reset the counter
5 Bus Timeout An EISA bus Master or Slave exceeds the allocated time on the bus A bus timeout occurs if
an EISA Master does not relinquish the bus (MREQ negated) within 64 BCLKS after it has been preempt-
ed (MACK negated) A bus timeout also occurs if a memory slave extends the cycle (CHRDY negated)
long enough to keep CMD asserted for more than 256 BCLKS The DMA controller does not cause a bus
timeout The ESC asserts RESDRV when a bus timeout occurs
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