82374EB Datasheet, PDF (82/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
3 4 3 ICW3 INITIALIZATION COMMAND WORD 3 (MASTER)
Register Location
Default Value
Attribute
Size
021h INT CNTRL-1
xxh
Write Only
8 Bits
The meaning of ICW3 differs between CNTRL-1 and CNTRL-2 On CNTRL-1 the master controller ICW3
indicates which CNTRL-1 IRQ line physically connects the INT output of CNTRL-2 to CNTRL-1 ICW3 must be
programmed to 04h indicating the cascade of the CNTRL-2 INT output to the IRQ 2 input of CNTRL-1
An interrupt request on IRQ2 causes CNTRL-1 to enable CNTRL-2 to present the interrupt vector address
during the second interrupt acknowledge cycle
Bit
Description
7 3 Cascade Interrupt Controller IRQs Bits 7 3 and bits 1 0 must be programmed to 0
10
2 Cascade Interrupt Controller IRQs Bit 2 must always be programmed to a 1 This bit indicates that
CNTRL-2 the slave controller is cascaded on interrupt request line two (IRQ 2 ) When an interrupt
request is asserted to CNTRL-2 the IRQ goes through the priority resolver After the slave controller
priority resolution is finished the INT output of CNTRL-2 is asserted However this INT assertion does
not go directly to the CPU Instead the INT assertion cascades into IRQ 2 on CNTRL-1 IRQ 2 must
go through the priority resolution process on CNTRL-1 If it wins the priority resolution on CNTRL-1
and the CNTRL-1 INT signal is asserted to the CPU the returning interrupt acknowledge cycle is really
destined for CNTRL-2 The interrupt was originally requested at CNTRL-2 so the interrupt
acknowledge is destined for CNTRL-2 and not a response for IRQ 2 on CNTRL-1
When an interrupt request from IRQ 2 wins the priority arbitration in reality an interrupt from
CNTRL-2 has won the arbitration Because bit 2 of ICW3 on the master is set to 1 the master knows
which identification code to broadcast on the internal cascade lines alerting the slave controller that it
is responsible for driving the interrupt vector during the second INTA pulse
3 4 4 ICW3 INITIALIZATION COMMAND WORD 3 (SLAVE)
Register Location
Default Value
Attribute
Size
INT CNTRL-2 port address-0A1h
xxh
Write Only
8 Bits
On CNTRL-2 (the slave controller) ICW3 is the slave identification code broadcast by CNTRL-1 from the
trailing edge of the first INTA pulse to the trailing edge of the second INTA pulse CNTRL-2 compares the
value programmed in ICW3 with the incoming identification code The code is broadcast over three ESC
internal cascade lines ICW3 must be programmed to 02h for CNTRL-2 When 010b is broadcast by CNTRL-1
during the INTA sequence CNTRL-2 assumes responsibility for broadcasting the interrupt vector during the
second interrupt acknowledge cycle
As an illustration consider an interrupt request on IRQ 2 of CNTRL-1 By definition a request on IRQ 2 must
have been asserted by CNTRL-2 If IRQ 2 wins the priority resolution on CNTRL-1 the interrupt acknowledge
cycle returned by the CPU following the interrupt is destined for CNTRL-2 not CNTRL-1 CNTRL-1 will see the
INTA signal and knowing that the actual destination is CNTRL-2 will broadcast a slave identification code
across the internal cascade lines CNTRL-2 will compare this incoming value with the 010b stored in ICW3
Following a positive decode of the incoming message from CNTRL-1 CNTRL-2 will drive the appropriate
interrupt vector onto the data bus during the second interrupt acknowledge cycle
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