82374EB Datasheet, PDF (50/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Bit
Description
28 16 Reserved
15 3 Fast Off IRQ 15 3 Enable (FIRQ 15 3 EN) These bits are used to prevent the system from
entering Fast Off and break any current powerdown state when the selected hardware interrupt
occurs When a bit^e1 (enabled) the corresponding interrupt causes a system event that re-loads
the Fast Off Timer and a break event that negates the STPCLK signal When a bit^e0 (disabled)
the corresponding interrupt does not re-load the Fast Off Timer or negate the STPCLK signal
2
Reserved
1 0 Fast Off IRQ 1 0 Enable (FIRQ 1 0 EN) These bits are used to prevent the system from entering
Fast Off and break any current powerdown state when the selected hardware interrupt occurs
When a bit^e1 the corresponding interrupt causes a system event that re-loads the Fast Off Timer
and a break event that negates the STPCLK signal When a bit^e0 (disabled) the corresponding
interrupt does not re-load the Fast Off Timer or negate the STPCLK signal
3 1 22 FTMR FAST OFF TIMER REGISTER
Address Offset
Default Value
Attribute
Size
A8h
0Fh
Read Write
8 Bits
For the 82374SB the Fast Off Timer is used to indicate (through an SMI) that the system has been idle for a
pre-programmed period of time The Fast Off Timer consists of a count-down timer and the value programmed
into this register is loaded into the Fast Off Timer when an enabled system event occurs When the timer
expires an SMI special cycle is generated When the Fast Off Timer is enabled (bit 3^e0 in the SMICNTL
Register) the timer counts down from the value loaded into this register The count time interval is one minute
When the Fast Off Timer reaches 00h an SMI is generated and the timer is re-load with the value programmed
into this register If an enabled system event occurs before the Fast Off Timer reaches 00h the Fast Off Timer
is re-loaded with the value in this register
NOTE
Before writing to the FTMR Register the Fast Off Timer must be stopped via bit 3 of the SMICNTL
Register In addition this register should NOT be programmed to 00h
Bit
Description
7 0 Fast Off Timer Value Bits 7 0 contain the starting count value A read from the FTMR Register
returns the value last written
3 1 23 SMIREQ SMI REQUEST REGISTER
Address Offset
Default Value
Attribute
Size
AA-ABh
00h
Read Write
16 Bits
For the 82374SB the SMIREQ Register contains status bits indicating the cause of an SMI When an enabled
event causes an SMI the ESC automatically sets the corresponding event’s status bit to 1 Software sets the
status bits to 0 by writing a 0 to them Only the ESC hardware can set status bits to a 1 Software
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