82374EB Datasheet, PDF (16/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
By using burst transactions to fill or flush these buffers if appropriate the PCEB maximizes bus efficiency For
example an EISA device could fill a Line Buffer with byte word or Dword transfers and The PCEB would use a
PCI burst cycle to flush the filled line to PCI memory
BIOS Timer
The PCEB has a 16 bit BIOS Timer The timer can be used by BIOS software to implement timing loops The
timer count rate is derived from the EISA clock (BCLK) and has an accuracy of g 1 ms
1 2 ESC Overview
The ESC implements system functions (e g timer counter DMA and interrupt controller) and EISA subsys-
tem control functions (e g EISA bus controller and EISA bus arbiter) The major functions provided by the
ESC are described in this section
EISA Controller
The ESC incorporates a 32-bit master and an 8-bit slave The ESC directly drives eight EISA slots without
external data or address buffering EISA system clock (BCLK) generation is integrated by dividing the PCI
clock (divide by 3 or divide by 4) and wait-state generation is provided The AENx and MACKx signals provide
a direct interface to four EISA slots and supports eight EISA slots with encoded AENx and MACKx signals
The ESC contains an 8-bit data bus (lower 8 bits of the EISA data bus) that is used to program the ESC’s
internal registers Note that for transfers between the PCI and EISA Buses the PCEB provides the data path
Thus the ESC does not require a full 32 bit data bus A full 32-bit address bus is provided and is used during
refresh cycles and for DMA operations
The ESC performs cycle translation between the EISA Bus and ISA Bus For mis-matched master slave
combinations the ESC controls the data swap logic that is located in the PCEB This control is provided
through the PCEB ESC interface
DMA Controller
The ESC incorporates the functionality of two 82C37 DMA controllers with seven independently programma-
ble channels Each channel can be programmed for 8 or 16 bit DMA device size and ISA-compatible type
‘‘A’’ type ‘‘B’’ or type ‘‘C’’ timings Full 32 bit addressing is provided The DMA controller is also responsible
for generating refresh cycles
The DMA controller supports an enhanced feature called scatter gather This feature provides the capability
of transferring multiple buffers between memory and I O without CPU intervention In scatter gather mode
the DMA can read the memory address and word count from an array of buffer descriptors located in main
memory called the scatter gather descriptor (SGD) table This allows the DMA controller to sustain DMA
transfers until all of the buffers in the SGD table are handled
Interrupt Controller
The ESC contains an EISA compatible interrupt controller that incorporates the functionality of two 82C59
Interrupt Controllers The two interrupt controllers are cascaded providing 14 external and two internal inter-
rupts
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