82374EB Datasheet, PDF (52/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
3 1 24 CTLTMRCLOCK SCALE STPCLK LOW TIMER
Address Offset
Default Value
Attribute
Size
ACh
00h
Read Write
8 Bits
For the 82374SB the value in this register defines the duration of the STPCLK asserted period when bit 2 in
the SMICNTL Register is set to 1 The value in this register is loaded into the STPCLK Timer when
STPCLK is asserted However the timer does not start until the Stop Grant Bus Cycle is received The
STPCLK timer counts using a 32 ms clock
Bit
Description
7 0 Clock Scaling STPCLK Low Timer Value Bits 7 0 define the duration of the STPCLK asserted
period during clock throttling
3 1 25 CTLTMRH CLOCK SCALE STPCLK HIGH TIMER
Address Offset
Default Value
Attribute
Size
AEh
00h
Read Write
8 Bits
For the 82374SB the value in this register defines the duration of the STPCLK negated period when bit 2 in
the SMICNTL Register is set to 1 The value in this register is loaded into the STPCLK Timer when
STPCLK is negated The STPCLK timer counts using a 32 ms clock
Bit
Description
7 0 Clock Scaling STPCLK High Timer Value Bits 7 0 define the duration of the STPCLK negated
period during clock throttling
3 2 DMA Register Description
The ESC contains DMA circuitry that incorporates the functionality of two 82C37 DMA controllers (DMA1 and
DMA2) The DMA registers control the operation of the DMA controllers and are all accessible from the EISA
Bus This section describes the DMA registers Unless otherwise stated a reset sets each register to its
default value The operation of the DMA is further described in Chapter 6 0 DMA Controller
3 2 1 DCOM COMMAND REGISTER
Register Location
Default Value
Attribute
Size
08h Channels 0-3
0D0h Channels 4-7
00h
Write Only
8 Bits
This 8-bit register controls the configuration of the DMA It is programmed by the microprocessor in the
Program Condition and is cleared by reset or a Master Clear instruction Note that disabling Channels 4-7 will
also disable Channels 0-3 since Channels 0-3 are cascaded onto Channel 4 The DREQ and DACK channel
assertion sensitivity is assigned by channel group not per individual Channel For priority resolution the DMA
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