82374EB Datasheet, PDF (120/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
5 3 4 EISA MASTER BACK-OFF
During EISA master transfer where the master and slave size is mis-matched the EISA master is required to
back-off the bus on the first falling edge of BCLK after START is negated The EISA master floats its
START BE 3 0 and data lines at this time This allows the ESC to performs translation cycle The master
must back-off the bus if a master slave data size mis-match is determined regardless if data size translation is
performed
At the end of the data size translation or transfer cycle control is transferred back to the bus master by the
ESC by driving EX32 and EX16 active on the falling edge of BCLK before the rising edge of BCLK that the
last CMD is negated An additional BCLK is added at the end of the transfer to allow the exchanging of cycle
control to occur
Figure 6 EISA Master Back Off Cycle
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