82374EB Datasheet, PDF (7/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

CONTENTS
3 5 3 PORT 92 REGISTER
3 5 4 LEISAMG LAST EISA BUS MASTER GRANTED REGISTER
3 6 Power Management Registers
3 6 1 APMC ADVANCED POWER MANAGEMENT CONTROL PORT
3 6 2 APMS ADVANCED POWER MANAGEMENT STATUS PORT
3 7 APIC Registers
3 7 1 IOREGSEL I O REGISTER SELECT REGISTER
3 7 2 IOWIN I O WINDOW REGISTER
3 7 3 APICID I O APIC IDENTIFICATION REGISTER
3 7 4 APICID I O APIC IDENTIFICATION REGISTER
3 7 5 APICARB I O APIC ARBITRATION REGISTER
3 7 6 IOREDTBL 15 0 I O REDIRECTION TABLE REGISTERS
4 0 ADDRESS DECODING
4 1 BIOS Memory Space
4 2 I O Addresses Contained Within The ESC
4 3 Configuration Addresses
4 4 X-Bus Peripherals
4 5 I O APIC Registers
5 0 EISA CONTROLLER FUNCTIONAL DESCRIPTION
5 1 Overview
5 2 Clock Generation
5 2 1 CLOCK STRETCHING
5 3 EISA Master Cycles
5 3 1 EISA MASTER TO 32-BIT EISA SLAVE
5 3 2 EISA MASTER TO 16-BIT ISA SLAVE
5 3 3 EISA MASTER TO 8-BIT EISA ISA SLAVES
5 3 4 EISA MASTER BACK-OFF
5 4 ISA Master Cycles
5 4 1 ISA MASTER TO 32- 16-BIT EISA SLAVE
5 4 2 ISA MASTER TO 16-BIT ISA SLAVE
5 4 3 ISA MASTER TO 8-BIT EISA ISA SLAVE
5 4 4 ISA WAIT STATE GENERATION
5 5 Mis-Match Cycles
5 6 Data Swap Buffer Control Logic
5 7 Servicing DMA Cycles
5 8 Refresh Cycles
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