82374EB Datasheet, PDF(40/208 Page) Intel Corporation

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82374EB Datasheet, PDF (40/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

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82374EB 82374SB

3 1 6 CLKDIV EISA CLOCK DIVISOR REGISTER

Address Offset

Default Value

Attribute

Size

4Dh

xx001000b

Read Write

8 Bits

This register is used to select the integer value used to divide the PCI clock (PCICLK) to generate the EISA

Bus Clock (BCLK) and enable disable the co-processor error support In addition for the 82374SB the

Bit

Description

7 6 Reserved

5 Co-processor Error The state of this bit determines if the FERR signal is connected to the ESC

internal IRQ13 interrupt signal If this bit is set to 1 the ESC will assert IRQ13 to the interrupt controller

if FERR signal is asserted If this bit is set to 0 then the FERR signal is ignored by the ESC (i e this

signal is not connected to any logic in the ESC)

4 82374EB Reserved

82374SB ABFULL (With IRQ12) When bit 4e0 the internal IRQ12 is directed to the interrupt

controller and transitions on ABFULL have no affect on this interrupt signal When bit 4e1 the

assertion of ABFULL is latched and directed to the internal IRQ12 signal in the following manner

If the interrupt controller is programmed for edge detect mode on IRQ12 a low-to-high transition is

generated on the internal IRQ12 signal Transitions on the IRQ12 input pin are not reflected on the

internal IRQ12 signal

If the interrupt controller is programmed for level-sensitive mode a high-to-low transition is

generated on the internal IRQ12 signal Transitions on the IRQ12 input pin are also reflected on the

internal IRQ12 signal

The latching of the ABFULL signal is cleared by an I O read of address 60h (no aliasing) or by a hard

reset

3 82374EB Reserved

82374SB Keyboard Full (KBFULL) This bit selects the edge-detect KBFULL function on the IRQ1

input signal When bit 3e0 IRQ1 is directed to the interrupt controller When bit 3e1 (default) IRQ1

is latched and directed to the interrupt controller The latched IRQ1 is cleared by an I O read of

address 60h (no aliasing) or by a hard reset

2 0 Clock Divisor These bits are used to select the integer that is used to divide the PCICLK down to

generate the BCLK Upon reset these bits are set to 000b (divisor of 4)

Bit 2 0

000

001

010

011

1xx

Divisor

4 (33 33 MHz)

3 (25 MHz)

Reserved

BCLK

8 33 MHz

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