82374EB Datasheet, PDF (184/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
12 7 Configuration RAM Interface
The ESC provides the control signals for 8 Kbytes of external configuration RAM The configuration RAM is
used for storing EISA configuration system parameters The configuration RAM is I O mapped between
location 0800h–08FFh Due to the I O address constraint (256 byte addresses for 8 Kbyte of RAM) the
configuration RAM is organized in 32 pages of 256 bytes each The I O port 0C00h is used to store the
configuration RAM page address The ESC integrates this port as Configuration RAM Page register During a
read or a write to the configuration RAM address space 0800h – 08FFh the ESC drives the configuration RAM
page address by placing the content of the Configuration RAM Page Address register bits 4 0 on the EISA
Address line LA 31 27 The ESC will also assert the CRAMRD signal or the CRAMWR signal for I O
read and write accesses to I O address 0800h – 08FFh The ESC will only generate the configuration RAM
page address and assert the CRAMRD signal and CRAMWR signal if the Peripheral Chip Select B register
bit 7 is set to 1
12 8 General Purpose Peripherals IDE Parallel Port and Serial Port Interface
The ESC provides three dual function pins (GPCS 2 0 ECS 2 0 ) The functionality of these pins is selected
through the configuration Mode Select register bit 4 If Mode Select register bit 4 is set to 0 the general
purpose chip select functionality is selected If Mode Select register bit 4 is set to 1 the encoded chip select
functionality is selected
In general purpose chip select mode the ESC generates three general purpose chip selects (GPCS 2 0 )
The decode for each general purpose chip selects is programmed through a set of three configuration regis-
ters General Purpose Chip Select x Base Low Address register General Purpose Chip Select x Base High
Address register and General Purpose Chip Select x Mask register Each General Purpose Peripheral can be
mapped anywhere in the 64 Kbytes of I O address The general purpose peripheral address range is program-
mable from 1 byte to 256 bytes with 2^{n granularity}
In encoded chip select mode (ESC 2 0 ) in addition to decoding the general purpose chip select 0 address
and general purpose chip select 1 address the ESC also decodes IDE Parallel Ports and Serial Ports
addresses The encoded chip select mode requires an external decoder like a F138 to generate the device
chip selects from the ESC 2 0 signals
The ESC generates encoded chip selects for two Serial Ports COMACS (ECS 2 0 ^e000) and COMBCS
(ESC 2 0 ^e001) The ESC supports Serial Port COM1 and Serial Port COM2 Accesses to Serial Port COM1
or Serial Port COM2 are individually programmed through Peripheral Chip Select B register bits 0 3 to gener-
ate a encoded chip select for COMACS or COMBCS
Figure 30 Encoded Chip Select Decoder Logic
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