82374EB Datasheet, PDF (24/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
2 4 DMA Signal Description
Pin Name
DREQ 7 5 3 0
DACK 7 5 3 0
EOP
Type
Description
in DMA REQUEST DREQ signals are either used to request DMA service from the
ESC or used to gain control of the ISA Bus by a ISA Bus master The active level
(high or low) is programmed in the Command registers When the Command
register bit 6 is programmed to 0 DREQ are asserted high otherwise the DREQ
are asserted low All inactive to active edges of DREQ are assumed to be
asynchronous The request must remain asserted until the appropriate DACK is
negated At power-up and after RESET these lines should be low (negated)
out DMA ACKNOWLEDGE DACK indicate that a request for DMA service from
the DMA subsystem has been recognized or that an ISA Bus master has been
granted the bus The level of the DACK lines when asserted may be
programmed to be either high or low This is accomplished by programming the
DMA Command register These lines should be used to decode the DMA slave
device with the IORC or IOWC line to indicate selection If used to signal
acceptance of a bus master request this signal indicates when it is legal to
assert MASTER16 If the DMA controller has been programmed for a timing
mode other than compatible mode and another device has requested the bus
and a 4 ms time has elapsed DACK will be negated and the transfer stopped
before the transfer is complete In this case the transfer will be restarted at the
next arbitration period in which the channel wins the bus Upon reset these lines
are negated
t s END OF PROCESS EOP pin acts in one of two modes and it is directly
connected to the TC line of the ISA Bus In the first mode EOP-In the pin is an
input and can be used by a DMA slave to stop a DMA transfer In the second
mode TC-Out it is used as a terminal count output by DMA slaves An active
pulse is generated when the byte counter reaches its last value
EOP-In Mode During DMA for all transfer types the EOP pin is sampled by the
ESC If it is sampled asserted the address bus is tristated and the transfer is
terminated
TC-Out Mode The EOP output will be asserted after a new address has been
output if the byte count expires with that transfer The EOP (TC) will stay
asserted until AEN is negated unless AEN is negated during an
autoinitialization EOP (TC) will be negated before AEN is negated during an
autoinitialization
Intout Mode In this mode the EOP signal has the same behavior as the
Chaining Interrupt or the Scatter-Gather interrupt to the host processor (IRQ13)
If a scatter-gather or chaining buffer is expired EOP will go active on the falling
edge of BCLK Only the currently active channel’s interrupt will be reflected on
this pin Other channel’s with active interrupts pending will not affect the EOP
pin
Whenever all the DMA channels are not in use the EOP pin is kept in output
mode and negated After reset the EOP pin is kept in output mode and negated
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