82374EB Datasheet, PDF (147/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Interval Timer 2 Counter 0 implements a fail safe timer Counter 0 generates NMI at regular intervals thus
preventing the system from locking up Counter 1 is not used Counter 2 is used to slow down the CPU by
means of pulse-width modulation The output of Timer 2 Counter 2 is tied to the SLOWH signal
Function
Gate
Clock In
Out
Gate
Clock In
Out
Gate
Clock In
Out
Table 20 Interval Timer Functions
Counter 0 System Timer
Always On
1 193 MHz(OSC 12)
INT-1 IRQ0
Counter 0 Fail-Safe Timer
Always On
0 298 MHz(OSC 48)
NMI Interrupt
Counter 1 Refresh Request
Always On
1 193 MHz(0SC 12)
Refresh Request
Counter 2
Programmable
Port 61h
1 193 MHz(OSC 12)
Speaker
Counter 2
Refresh Request
8 MHz (BCLK)
CPU Speed Control (SLOWH )
8 1 Interval Timer Address Map
Table 21 shows the I O address map of the interval timer counters
Table 21 Interval Timer I O Address Map
I O Port Address
Register Description
040h
Timer 1 System Timer (Counter 0)
041h
Timer 1 Refresh Request (Counter 1)
042h
Timer 1 Speaker Tone (Counter 2)
043h
Timer 1 Control Word Register
048h
Timer 2 Fail-Safe Timer (Counter 0)
049h
Timer 2 Reserved
04Ah
Timer 2 CPU Speed Control (Counter 2)
04Bh
Timer 2 Control Word Register
Timer 1 Counter 0 System Timer
This counter functions as the system timer by controlling the state of IRQ 0 and is typically programmed for
Mode 3 operation The counter produces a square wave with a period equal to the product of the counter
period (838 ns) and the initial count value The counter loads the initial count value one counter period after
software writes the count value to the counter I O address The counter initially asserts IRQ 0 and decre-
ments the count value by two each counter period The counter negates IRQ 0 when the count value reaches
0 It then reloads the initial count value and again decrements the initial count value by two each counter
period The counter then asserts IRQ 0 when the count value reaches ‘‘0’’ reloads the initial count value and
repeats the cycle alternately asserting and negating IRQ 0
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