82374EB Datasheet, PDF (18/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
The following notations are used to describe the signal type
in
Input is a standard input-only signal
out Totem Pole Output is a standard active driver
o d Open Drain Input Output
t s Tri-State is a bi-directional tri-state input output pin
sts
Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agent at a
time The agent that drives a s t s pin low must drive it high for at least one clock before letting it float
A new agent can not start driving a s t s signal any sooner than one clock after the previous owner tri-
states it A pull-up sustains the inactive state until another agent drives it and is provided by the central
resource
NOTE
During a hard reset INTR NMI IGNNE SMI (on 82374SB) ALTRST STPCLK (on 82374SB)
and ALTA20 are driven low to prevent problems associated with 5V 3 3V power sequencing Any
outputs of the ESC that are directed to a 3 3V CPU must be driven through a 5V to 3 3V translator
2 1 PCI Local Bus Interface Signals
Pin Name Type
Description
PCICLK
in PCI CLOCK PCICLK provides timing for all transactions on the PCI bus The ESC uses
the PCI Clock (PCICLK) to generate EISA Bus Clock (BCLK) The PCICLK is divided by
3 or 4 to generate the BCLK The EISA Bridge supports PCI Clock frequencies of
25 MHz through 33 MHz
PERR
in PARITY ERROR PERR indicates a data parity error PERR may be pulsed active
by any agent that detects an error condition Upon sampling PERR active the ESC
generates an NMI interrupt to the CPU
SERR
in SYSTEM ERROR SERR may be pulsed active by any agent that detects an error
condition Upon sampling SERR active the ESC generates an NMI interrupt to the
CPU
RESET
in SYSTEM RESET RESET forces the entire ESC chip into a known state All internal
ESC state machines are reset and all registers are set to their default values RESET
may be asynchronous to PCICLK when asserted or negated Although asynchronous
negation must be a clean bounce-free edge The ESC uses RESET to generate
RSTDRV signal
2 2 EISA Bus Interface Signals
Pin Name Type
Description
BCLKOUT out EISA BUS CLOCK OUTPUT BCLKOUT is typically buffered to create EISA Bus Clock
(BCLK) The BCLK is the system clock used to synchronize events on the EISA ISA
bus The BCLKOUT is generated by dividing the PCICLK The ESC uses a divide by 3
or divide by 4 to generate the BCLKOUT
BCLK
in EISA BUS CLOCK The ESC uses BCLK to synchronize events on the EISA bus The
ESC generates or samples all the EISA ISA bus signals on either the rising or the
falling edge of BCLK
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