82374EB Datasheet, PDF (11/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
1 0 ARCHITECTURAL OVERVIEW
The PCI-EISA bridge chip set provides an I O subsystem core for the next generation of high-performance
personal computers (e g those based on the Intel486^TM or Pentium processors) System designers can take
advantage of the power of the PCI (Peripheral Component Interconnect) for the local I O bus while maintain-
ing access to the large base of EISA and ISA expansion cards and corresponding software applications
Extensive buffering and buffer management within the PCI-EISA bridge ensures maximum efficiency in both
bus environments
The chip set consists of two components the 82375EB SB PCI-EISA Bridge (PCEB) and the 82374EB SB
EISA System Component (ESC) These components work in tandem to provide an EISA I O subsystem
interface for personal computer platforms based on the PCI standard This section provides an overview of the
PCI and EISA Bus hierarchy followed by an overview of the PCEB and ESC components
Bus Hierarchy Concurrent Operations
Figure 1 shows a block diagram of a typical system using the PCI-EISA Bridge chip set The system contains
three levels of buses structured in the following hierarchy
 Host Bus as the execution bus
 PCI Bus as a primary I O bus
 EISA Bus as a secondary I O bus
This bus hierarchy allows concurrency for simultaneous operations on all three bus environments Data buffer-
ing permits concurrency for operations that cross over into another bus environment For example a PCI
device could post data into the PCEB permitting the PCI Local Bus transaction to complete in a minimum time
and freeing up the PCI Local Bus for further transactions The PCI device does not have to wait for the transfer
to complete to its final destination Meanwhile any ongoing EISA Bus transactions are permitted to complete
The posted data is then transferred to its EISA Bus destination when the EISA Bus is available The PCI-EISA
Bridge chip set implements extensive buffering for PCI-to-EISA and EISA-to-PCI bus transactions In addition
to concurrency for the operations that cross bus environments data buffering allows the fastest operations
within a particular bus environment (via PCI burst transfers and EISA burst transfers)
The PCI Local Bus with 132 MByte sec and EISA with 33 MByte sec peak data transfer rate represent bus
environments with significantly different bandwidths Without buffering transfers that cross the single bus
environment are performed at the speed of the slower bus Data buffers provide a mechanism for data rate
adoption so that the operation of the fast bus environment (PCI) i e usable bandwidth is not significantly
impacted by the slower bus environment (EISA)
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