82374EB Datasheet, PDF (151/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
One precaution is worth noting If a Counter is programmed to read write two-byte counts a program must not
transfer control between reading the first and second byte to another routine which also reads from that same
Counter Otherwise an incorrect count will be read
Read Back Command
The third method uses the Read-Back command The Read-Back command is used to determine the count
value programmed mode and current states of the OUT pin and Null Count flag of the selected counter or
counters The Read-Back command is written to the Control Word register which causes the current states of
the above mentioned variables to be latched The value of the counter and its status may then be read by I O
access to the counter address
The read-back command may be used to latch multiple counter output latches (OL) by setting the COUNT
bit D5^e0 and selecting the desired counter(s) This single command is functionally equivalent to several
counter latch commands one for each counter latched Each counter’s latched count is held until it is read (or
the counter is reprogrammed) Once read a counter is automatically unlatched The other counters remain
latched until they are read If multiple count read-back commands are issued to the same counter without
reading the count all but the first are ignored i e the count which will be read is the count at the time the first
read-back command was issued
The read-back command may also be used to latch status information of selected counter(s) by setting
STATUS bit D4^e0 Status must be latched to be read The status of a counter is accessed by a read from
that counter’s I O port address
If multiple counter status latch operations are performed without reading the status all but the first are ignored
The status returned from the read is the counter status at the time the first status read-back command was
issued
Both count and status of the selected counter(s) may be latched simultaneously by setting both the COUNT
and STATUS bits 5 4 ^e00b This is functionally the same as issuing two consecutive separate read-back
commands The above discussions apply here also Specifically if multiple count and or status read-back
commands are issued to the same counter(s) without any intervening reads all but the first are ignored
If both count and status of a counter are latched the first read operation from that counter will return the
latched status regardless of which was latched first The next one or two reads (depending on whether the
counter is programmed for one or two type counts) return the latched count Subsequent reads return un-
latched count
9 0 INTERRUPT CONTROLLER
The ESC provides an EISA compatible interrupt controller which incorporates the functionality of two 82C59
interrupt controllers The two controllers are cascaded so that 14 external and two internal interrupts are
possible The master interrupt controller provides IRQ 7 0 and the slave interrupt controller provides
IRQ 15 8 (Figure 19) The two internal interrupts are used for internal functions only and are not available at
the chip periphery IRQ2 is used to cascade the two controllers together and IRQ0 is used as a system timer
interrupt and is tied to Interval Timer 1 Counter 0 The remaining 14 interrupt lines (IRQ1 IRQ3-IRQ15) are
available for external system interrupts Edge or level sense selection is programmable on a by-controller
basis
The Interrupt Controller consists of two separate 82C59 cores Interrupt Controller 1 (CNTRL-1) and Interrupt
Controller 2 (CNTRL-2) are initialized separately and can be programmed to operate in different modes The
default settings are 80x86 Mode Edge Sensitive (IRQ0-15) Detection Normal EOI Non-Buffered Mode
Special Fully Nested Mode disabled and Cascade Mode CNTRL-1 is connected as the Master Interrupt
Controller and CNTRL-2 is connected as the Slave Interrupt Controller
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