82374EB Datasheet, PDF (183/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
The ESC asserts the KYBDCS signal for I O cycles to addresses 60h (82374EB SB) 62h (82374EB only)
64h (82374EB SB) and 66h (82374EB only) if the Peripheral Chip Select A register bit 1 is set to 1 The ESC
uses the ABFULL signal to internally generate an interrupt request to the integrated Interrupt Controller on the
IRQ12 line if EISA Clock Divisor register bit 4 is set to 1 (Mouse Interrupt Enable) A low to high transition on
the ABFULL signal is internally latched by the ESC The high level on this latch remains until a write to I O port
60h is detected or the ESC is reset
The ALTRST is used to reset the CPU under software control The ESC ALTRST signal needs to be
AND’ed externally with the reset signal from the keyboard controller A write to the System Control Register
(092h) bit 0 to set the bit to a 1 from a 0 causes the ESC to pulse the ALTRST signal ALTRST is asserted
for approximately 4 BCLKs The ESC will not pulse the ALTRST signal if bit 0 has previously been set to a 1
12 5 Real Time Clock
The ESC provides a glueless interface for the Real Time Clock in the system The ESC provides a Real Time
Clock Address Latch Enable signal (RTCALE) a Real Time Clock read Strobe(RTCRD ) and a Real Time
Clock Write strobe (RTCWR ) The ESC pulses the RTCALE signal asserted for one and a half BCLKs when
an I O write to address 70h is detected The ESC asserts RTCRD signal and RTCWR signal for I O read
and write accesses to address 71h respectively
The ESC also supports the power on password protection through the Real Time Clock The power on
password protection is enabled by setting the System Control register 092h bit 3 to a 1 The ESC does not
assert RTCRD signal or RTCWR signal for I O cycles to 71h if the access are addressed to Real Time
Clock addresses (write to 70h) 36h to 3Fh if the power on password protection is enabled
12 6 Floppy Disk Control Interface
The ESC supports interface to the 82077(SL) floppy disk controller chip The ESC provides a Floppy Disk
Controller Chip Select signal (FDCCS ) The ESC also provides a buffered Drive Interface (DSKCHG )
signal In addition the ESC generates the control for the disk light
The ESC supports both the primary address range (03F0h – 03F7h) and secondary address range (0370h –
0377h) of the Floppy Disk Controller The state of Peripheral Chip Select A register bit 5 determines which
address range is decoded by the ESC as access to Floppy Disk Controller If bit 5 is set to 0 the ESC will
decode the primary Floppy Disk Controller address range If bit 5 is set to 1 the ESC will decode the second-
ary Floppy Disk Controller address range
The ESC supports the Drive Interface signal During I O accesses to address 03F7h (primary) or 0377h
(secondary) the ESC drives the inverted state of the DSKCHG signal on to the SD7 data line The ESC uses
the DSKCHG signal to determine if the Floppy Disk Controller is present on the X-Bus If the DSKCHG
signal is samples low during reset the ESC will disable Floppy Disk Controller support
The ESC also supports the Disk Light function by generating the DLIGHT signal If System Control 092h
register bit 6 or bit 7 is set to a 1 the ESC will assert the DLIGHT signal
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