82374EB Datasheet, PDF (133/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
6 4 2 TYPE ‘‘A’’ TIMING
Type ‘‘A’’ timing is provided to allow shorter cycles to EISA memory (Note Main memory behaves like EISA
memory because the PCEB has an EISA slave interface ) Type ‘‘A’’ timing runs at 7 BCLKs (840 ns single
cycle) and 6 BCLKs (720 ns cycle) during the repeated portion of a Block or Demand mode transfer Type ‘‘A’’
timing varies from compatible timing primarily in shortening the memory operation to the minimum allowed by
system memory The I O portion of the cycle (data setup on write I O read access time) is the same as with
compatible cycles The actual active command time is shorter but it is expected that the DMA devices which
provide the data access time or write data setup time should not require excess IORC or IOWC command
active time Because of this most DMA devices should be able to use type ‘‘A’’ timing
Figure 12 Type ‘‘A’’ DMA Read Transfers (6 BCLKS)
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