82374EB Datasheet, PDF (20/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Pin Name
EX32
EX16
START
CMD
EXRDY
SLBURST
Type
Description
o d EISA 32 BIT DEVICE DECODE EX32 signal is asserted by a 32-bit EISA slave
device EX32 assertion indicates that an EISA device has been selected as a slave
and the device has a 32-bit data bus size The ESC uses this signal as an input as
part of its slave decode to determine if data size translation and or cycle translation
is required EX32 is an output of the ESC during the last portion of the mis-matched
cycle This is an indication to the backed-off EISA master that the data translation
has been completed The backed-off EISA master uses this signal to start driving the
EISA bus again
o d EISA 16-BIT DEVICE DECODE EX16 signal is asserted by a 16-bit EISA slave
device EX16 assertion indicates that an EISA device has been selected as a slave
and the device has a 16 bit data bus size The ESC uses this signal as an input as
part of its slave decode to determine if data size translation and or cycle translation
is required EX16 is an output of the ESC during the last portion of the mis-matched
cycle This is an indication to the backed-off EISA master that the data translation
has been completed The backed-off EISA master uses this signal to start driving the
EISA bus again
t s START CYCLE START signal provides timing control at the start of an EISA cycle
START is asserted for one BCLK START is an input to the ESC during EISA
master cycles except portions of the EISA master to mis-matched slave cycles where
it becomes an output During ISA DMA and Refresh cycles START is an output
out COMMAND CMD signal provides timing control within an EISA cycle The ESC is a
central resource of the CMD signal and the ESC generates CMD during all EISA
cycles CMD is asserted from the rising edge of BCLK simultaneously with the
negation of START and remains asserted until the end of the cycle
o d EISA READY EXRDY signal is deasserted by EISA slave devices to add wait states
to a cycle EXRDY is an input to the ESC for EISA master cycles ISA master cycles
and DMA cycles where an EISA slave has responded with EX32 or EX16
asserted The ESC samples EXRDY on the falling edge of BCLK after CMD is
asserted (except during DMA compatible cycles) During DMA compatible cycles
EXRDY is sampled on the second falling edge of BCLK after CMD is driven active
For all types of cycles if EXRDY is sampled inactive the ESC keeps sampling it on
every falling edge of BCLK EXRDY is an output for EISA master cycles decoded as
accesses to the ESC internal registers ESC forces EXRDY low for one BCLK at the
start of a potential DMA burst write cycle to insure that the initial write data is held
long enough to be sampled by the memory slave
in SLAVE BURST SLBURST signal is asserted by an EISA slave to indicate that the
device is capable of accepting EISA burst cycles The ESC samples SLBURST on
the rising edge of BCLK at the end of START for all EISA cycles During DMA
cycles the ESC samples SLBURST twice once on the rising edge of BCLK at the
beginning of START and again on the rising edge of BCLK at the end of START
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