82374EB Datasheet, PDF (173/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Lowest Priority (LP) without Focus Processor (FP) Message
This message format is used to deliver an interrupt in the lowest priority mode in which it does not have a
Focus Processor Cycles 1 through 20 for this message are the same as for the Short Message discussed
above Status cycle 19 identifies if there is not a Focus processor (00) and a status value of 11 in cycle 20
indicates the need for lowest priority arbitration
Cycle 21 through 28 are used to arbitrate for the lowest priority processor The processors that take part in the
arbitration drive their processor priority on the bus Only the local APICs that have ‘‘free interrupt slots’’
participate in the lowest priority arbitration
Cycle 29 through 32 are used to break a tie in case two or more processors have lowest priority The bus
arbitration IDs are used to break the tie
Cycle 33 is an additional status cycle driven by the accepting local APIC By receiving 10 during this cycle the
sending I O APIC knows that there was a local APIC left after LP arbitration Otherwise the message is
retried Cycle 34 is an idle cycle
Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Table 33 Lowest Priority without Focus Processor Message
Bit 1
Bit 0
0
1
0 1 ^e normal 1 1 ^e EOI
ArbID3
0
Arbitration ID bits 3 through 0
ArbID2
0
ArbID1
0
ArbID0
0
DM
M2
DM ^e Destination mode
M1
M0
M2 – M0 ^e Delivery mode
L
TM
L ^e Level TM ^e Trigger Mode
V7
V6
V7 – V0 ^e Interrupt Vector
V5
V4
V3
V2
V1
V0
D7
D6
Destination
D5
D4
D3
D2
D1
D0
C
C
Checksum for cycles 6-16
0
0
Postamble
A
A
Status cycle 0
A1
A1
Status cycle 1
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