82374EB Datasheet, PDF (191/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
13 4 Stop Grant Special Cycle
The Host-Bridge (e g PCMC) translates the CPU’s stop grant cycle into a PCI special cycle The PCEB
recognizes the stop grant PCI special cycle and asserts STPGNT low to ESC for one PCICLK The ESC does
not start the STPCLK low timer until STPGNT is asserted
During Halt or Autohalt state the P54C does not respond to STPCLK assertion with a stop grant cycle
However during this state an INTR SMI or NMI assertion causes the CPU to exit the halted state and
eventually recognize the STPCLK assertion with a stop grant cycle The system design must guarantee that
INTR SMI and NMI assertion is not blocked outside of the chipset while STPCLK is asserted Otherwise
a potential deadlock situation will exist
13 5 Dual-Processor Power Management Support
Figure 35 depicts the power management support for dual-processor (DP) or P54CT upgrade processor
configuration The input signals of SMI STPCLK and NMI of both OEM and upgrade sockets are tied
together
Figure 35 Dual Processor System Configuration
290476 – E2
13 5 1 SMI DELIVERY MECHANISM
For Uni or CT upgrade processor system configuration SMI can either be delivered through the ESC SMI
signal or I O APIC For the P54C CM Dual-processor configuration SMI should be delivered through I O
APIC only Ideally the OS will put the CM processor in Autohalt after the CM processor received a Fast-Off
SMI The CM processor will wake up if any non-masked system events occur
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