82374EB Datasheet, PDF (23/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Pin Name
NOWS
OSC
RSTDRV
REFRESH
AEN
AEN 4 1
EAEN 4 1
Type
Description
o d ZERO WAIT STATES NOWS indicates that an peripheral device wishes to
execute a zero wait-state bus cycle (the normal default 16-bit ISA bus memory or I O
cycle is 3 BCLKS) When NOWS is asserted a 16-bit memory cycle will occur in
two BCLKs and a 16-bit I O cycle will occur in three BCLKs When NOWS is
asserted by an 8-bit device the default 6 BCLKs cycle is shortened to 4 or 5 BCLKs
NOWS is an input when the ESC performing bus translation cycles NOWS is an
output when the ESC internal registers are accessed
If CHRDY and NOWS are both asserted during the same clock then NOWS will
be ignored and wait-states will be added as a function of CHRDY (CHRDY has
precedence over NOWS )
in OSCILLATOR OSC is the 14 31818 MHz signal with 50% duty cycle OSC is used
by the ESC timers
out RESET DRIVE RSTDRV is asserted by the ESC An asserted RSTDRV causes a
hardware reset of the devices on the ISA Bus RSTDRV is asserted whenever the
RESET input to the ESC is asserted
t s REFRESH REFRESH is used by the ESC as an output to indicate when a refresh
cycle is in progress It should be used to enable the SA 15 0 address to the row
address inputs of all banks of dynamic memory on the ISA bus so that when MRDC
goes active the entire expansion bus dynamic memory is refreshed Memory slaves
must not drive any data onto the bus during refresh and should not add wait states
since this will affect the entire system throughput As an output this signal is driven
directly onto the ISA bus This signal is an output only when the ESC DMA Refresh is
a master on the bus responding to an internally generated request for Refresh Upon
RESET this pin will tristate Note that address lines 15 8 are driven during refresh
but the value is meaningless and is not used to refresh ISA bus memory
REFRESH may asserted by an expansion bus adapter acting as a 16-bit ISA bus
master
out ADDRESS ENABLE AEN is driven high for Bus master cycles AEN is driven
low for DMA cycles and Refresh cycles AEN is used to disable I O devices from
responding to DMA and Refresh cycles System designs which do not used the slots
specific AENs (AEN 4 1 EAEN 4 1 ) provided by the ESC can use the AEN signal
to generate their own slot specific AENs
out SLOT SPECIFIC ADDRESS ENABLE ENCODED SLOT SPECIFIC ADDRESS
ENABLE These pins have a slightly different function depending on the ESC
configuration (Mode Select register bit 1 and bit 0)
Slot Specific Address Enable If the ESC is programmed to support 4 EISA slots
these signals function as Slot Specific Address Enables (AEN 4 1 )
Encoded Slot Specific Address Enable If the ESC has been programmed to support
more than 4 EISA slots then these signals behave as Encoded Address Enables
(EAEN 4 1 ) A discrete decoder is required to generate slot specific AENs
Refer to Section 5 8 1 AEN GENERATION for a detailed description of these signals
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