82374EB Datasheet, PDF (138/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Figure 16 Link List Example
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6 7 Register Functionality
See Section 3 2 for detailed information on register programming bit definitions and default values functions
after a reset
DMA Channel 4 is used to cascade the two DMA controllers together and should not be programmed for any
mode other than cascade The Mode register for Channel 4 will default to cascade mode Special attention
should also be take when programming the Command and Mask registers as related to Channel 4 (refer to the
Command and Mask register descriptions Section 3 2)
6 7 1 ADDRESS COMPATIBILITY MODE
Whenever the DMA is operating in Address Compatibility mode the addresses do not increment or decrement
through the High and Low Page registers and the high page register is set to 00h This is compatible with the
82C37 and Low Page register implementation used in the PC AT This mode is set when any of the lower three
address bytes of a channel are programmed If the upper byte of a channel’s address is programmed last the
channel will go into Extended Address Mode In this mode the high byte may be any value and the address
will increment or decrement through the entire 32-bit address
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