82374EB Datasheet, PDF (118/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
If EX16 is asserted a 32-bit EISA master backs-off the bus by floating BE 3 0 and START (see Section
5 3 4) The ESC acts as a central resource for the EISA master in this case and takes over the mastership of
the EISA bus by deriving START CMD and the appropriate byte enables The ESC generates the neces-
sary translation cycles for the EISA master and returns the bus ownership to the master by asserting EX32
and EX16 The ESC monitors the EXRDY signal on the EISA bus to determine when to negate the CMD
An EISA Slave can extend the cycle by negating EXRDY EISA specification require that EXRDY not be held
negated for more than 2 5 ms A burstable EISA slave will assert the SLBURST signal the same time when
its address is decoded The EISA master will sample SLBURST and assert MSBURST if it is capable of
bursting The ESC keeps the CMD asserted during a burst EISA transfer The ESC deasserts CMD to
indicate the end of the burst transfer after the EISA master deasserts MSBURST
Figure 4 Standard EISA Master to EISA Slave Cycle
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