82374EB Datasheet, PDF (36/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
3 1 1 ESCID ESC ID REGISTER
Address Offset
Default Value
Attribute
Size
02h
00h
Read Write
8 Bits
Since the ESC configuration registers are accessed by the index addressing mechanism using I O Ports 22h
and 23h it is possible that another device in the system might use the same approach for configuration In
order to avoid contention with similar index register devices the ID register must be written with 0Fh The ESC
will not respond to accesses to any other configuration register until the ID byte has been written in the ESC ID
Register
Bit
Description
7 0 ESC ID Byte These bits must be written to a value of 0Fh before the ESC will respond to any other
configuration register access After a reset has occurred all of the configuration registers except this
register are disabled
3 1 2 RID REVISION ID REGISTER
Address Offset
Default Value
Attribute
Size
08h
02h (82374EB A-2 stepping)
03h (82374SB B-0 stepping)
Read only
8 Bits
This 8-bit register contains device stepping information Writes to this register have no effect
Bit
Description
7 0 Revision ID Byte These bits contain the stepping information about the device The register is
hardwired to the default value during manufacturing The register is read only Writes have no effect on
the register value
3 1 3 MS MODE SELECT REGISTER
Address Offset
Default Value
Attribute
Size
40h
20h
Read Write
8 Bits
This register selects the various functional modes of the ESC
Bit
Description
7 Reserved
6 MREQ 7 4 PIRQ 3 0 Enable This bit enables the selected (MREQ 7 4 PIRQ 3 0
functionality 1^eEnabled 0^eDisabled
5 Configuration RAM Address This bit is used to enable or disable the configuration RAM Page
Address (CPG 4 0 ) generation If this bit is set to 1 accesses to the configuration RAM space will
generate the RAM page address on the LA 31 27 pins If this bit is set to 0 the CPG 4 0 signals will
not be activated The default for this bit is 1
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