82374EB Datasheet, PDF (163/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
9 7 2 OPERATION CONTROL WORDS (OCWS)
After the Initialization Command Words (ICWs) are programmed into the Interrupt Controller the chip is ready
to accept interrupt requests at its input lines However Interrupt Controller operation can be dynamically
modified to fit specific software hardware expectations Different modes of operation are dynamically selected
following initialization through the use of Operation Command Words (OCWs)
9 8 Interrupt Masks
9 8 1 MASKING ON AN INDIVIDUAL INTERRUPT REQUEST BASIS
Each Interrupt Request input can be masked individually by the Interrupt Mask register (IMR) This register is
programmed through OCW1 Each bit in the IMR masks one interrupt channel if it is set to a ‘‘1’’ Bit 0 masks
IRQ0 bit 1 masks IRQ1 and so forth Masking an IRQ channel does not effect the other channel’s operation
with one notable exception Masking IRQ 2 on CNTRL-1 will mask off all requests for service from CNTRL-2
The CNTRL-2 INTR output is physically connected to the CNTRL-1 IRQ 2 input
9 8 2 SPECIAL MASK MODE
Some applications may require an interrupt service routine to dynamically alter the system priority structure
during its execution under software control For example the routine may wish to inhibit lower priority requests
for a portion of its execution but enable some of them for another portion
The difficulty here is that if an Interrupt Request is acknowledged and an End of Interrupt command did not
reset its IS bit (i e while executing a service routine) the Interrupt Controller would have inhibited all lower
priority requests with no easy way for the routine to enable them
The Special Mask Mode enables all interrupts not masked by a bit set in the Mask Register Interrupt service
routines that require dynamic alteration of interrupt priorities can take advantage of the Special Mask Mode
For example a service routine can inhibit lower priority requests during a part of the interrupt service then
enable some of them during another part
In the Special Mask Mode when a mask bit is set in OCW1 it inhibits further interrupts at that level and
enables interrupts from all other levels (lower as well as higher) that are not masked
Thus any interrupts may be selectively enabled by loading the Mask register with the appropriate pattern
Without Special Mask Mode if an interrupt service routine acknowledges an interrupt without issuing an EOI to
clear the IS bit the interrupt controller inhibits all lower priority requests The Special Mask Mode provides an
easy way for the interrupt service routine to selectively enable only the interrupts needed by loading the Mask
register
The special Mask Mode is set by OCW3 where SSMM^e1 SMM^e1 and cleared where SSMM^e1 SMM^e0
9 9 Reading The Interrupt Controller Status
The input status of several internal registers can be read to update the user information on the system The
Interrupt Request Register (IRR) and In-Service Register (ISR) can be read via OCW3 as discussed in Section
3 7 The Interrupt Mask Register (IMR) is read via a read of OCW1 as discussed in Section 3 7 Here are brief
descriptions of the ISR the IRR and the IMR
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