82374EB Datasheet, PDF (26/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Pin Name
MACK 3 0
EMACK 3 0
Type
Description
out MASTER ACKNOWLEDGE ENCODED MASTER ACKNOWLEDGE These pins
behave in one of two modes depending on the state of the Mode Select register bit
1 and bit 0 If the ESC is programmed to support 4 EISA slots then these pins are
used as MACK If the ESC is programmed to support more than 4 EISA slots
then these pins are used as EMACK
Master Acknowledge The MACK 3 0 signals are asserted from the rising edge
of BCLK at which time the bus master may begin driving the LA BE M IO
and W R lines on the next falling edge of BCLK MACK will stay asserted until
the rising edge of BCLK when MREQ is sampled negated MACK is sampled by
EISA Bus masters on the falling edge of BCLK If another device has requested the
bus MACK will be negated before MREQ is negated When MACK is
negated the granted device has a maximum of 8 ms to negate MREQ and begin
a final bus cycle The ESC may negate the MACK signal a minimum of one BCLK
after asserting it if another device (or refresh) is requesting the bus Upon reset
MACK is negated
Encoded Master Acknowledge EMACK behaves like MACK The difference
is that a discrete decoder is required to generate MACK for the EISA Bus
masters
Refer to Section 5 8 2 MACK Generation for details
2 6 Timer Unit Signal
Pin Name Type
Description
SPKR
out SPEAKER DRIVE SPKR is the output of Timer 1 Counter 2 and is ‘‘ANDed’’ with Port
061h bit 1 to provide Speaker Data Enable This signal drives an external speaker
driver device which in turn drives the ISA system speaker SPKR has a 24 mA drive
capability Upon reset its output state is low
SLOWH
out SLOW DOWN CPU SLOWH is the output of Timer 2 Counter 2 This counter is used
to slow down the main CPU of its execution via the CPU’s HOLD pin by pulse width
modulation The first read of I O register in the 048h-04Bh range will enable SLOWH
signal to follow the output of the Timer 2 Counter 2 Upon reset SLOWH is negated
Hardware Reset (Strapping Option)
During hardware reset this signal is an input and the level on the pin at the end of the
reset sequence determines where BIOS resides A high level indicates that BIOS
resides on the X-Bus and a low level indicates that BIOS resides on the ISA Bus The
status is used by the ESC to control the X-Bus transceivers during BIOS access
NOTE
For the 82374EB this pin has an internal weak pull-up of approximately 8 KX
For proper configuration of the BIOS location during reset a weak external pull-
down resistor (approx 500X) must be connected to this pin
An external pull-down resistor is not needed for the 82374SB
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