82374EB Datasheet, PDF (159/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
There are two forms of EOI commands Specific and Non-Specific When the Interrupt Controller is operated in
modes which preserve the fully nested structure it can determine which IS bit to reset on EOI When a Non-
Specific EOI command is issued the Interrupt Controller will automatically reset the highest IS bit of those that
are set since in the fully nested mode the highest IS level was necessarily the last level acknowledged and
serviced A non-specific EOI can be issued with OCW2 (EOI^e1 SL^e0 R^e0)
When a mode is used which may disturb the fully nested structure the Interrupt Controller may no longer be
able to determine the last level acknowledged In this case a Specific End of Interrupt must be issued which
includes as part of the command the IS level to be reset A specific EOI can be issued with OCW2 (EOI^e1
SL^e1 R^e0 and L0-L2 is the binary level of the IS bit to be reset)
It should be noted that an IS bit that is masked by an IMR bit will not be cleared by a non-specific EOI if the
Interrupt Controller is in the Special Mask Mode
9 5 2 AUTOMATIC END OF INTERRUPT (AEOI) MODE
If AEOI^e1 in ICW4 then the Interrupt Controller will operate in AEOI mode continuously until reprogrammed
by ICW4 Note that reprogramming ICW4 implies that ICW1 ICW2 and ICW3 must be reprogrammed first in
sequence In this mode the Interrupt Controller will automatically perform a non-specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse Note that from a system standpoint this mode should be
used only when a nested multilevel interrupt structure is not required within a single Interrupt Controller The
AEOI mode can only be used in a master Interrupt Controller and not a slave (on CNTRL-1 but not CNTRL-2)
9 6 Modes Of Operation
9 6 1 FULLY NESTED MODE
This mode is entered after initialization unless another mode is programmed The interrupt requests are
ordered in priority from 0 through 7 (0 being the highest) When an interrupt is acknowledged the highest
priority request is determined and its vector placed on the bus Additionally a bit of the Interrupt Service
register (IS 0 7 ) is set This IS bit remains set until the microprocessor issues an End of Interrupt (EOI)
command immediately before returning from the service routine Or if the AEOI (Automatic End of Interrupt)
bit is set this IS bit remains set until the trailing edge of the second internal INTA While the IS bit is set all
further interrupts of the same or lower priority are inhibited while higher levels will generate an interrupt (which
will be acknowledged only if the microprocessor internal Interrupt enable flip-flop has been re-enabled through
software)
After the initialization sequence IRQ0 has the highest priority and IRQ7 the lowest Priorities can be changed
as will be explained in the rotating priority mode
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