82374EB Datasheet, PDF (49/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Bit
Description
2 IRQ4 SMI Enable (COM2 COM4 Interrupt or Mouse) Thsi bit enables the IRQ4 signal to generate
an SMI When bit 1^e1 asserting the IRQ3 input signal generates an SMI When bit 2^e0 asserting
IRQ4 does not generate an SMI
1 IRQ3 SMI Enable (COM1 COM3 Interrupt or Mouse) This bit enables the IRQ3 signal to generate
an SMI When bit 1^e1 asserting the IRQ3 input signal generates an SMI When bit 1^e0 asserting
IRQ3 does not generate an SMI
0 IRQ1 SMI Enable (Keyboard Interrupt) This bit enables the IRQ1 signal to generate an SMI When
bit 0^e1 asserting the IRQ1 input signal generates an SMI When bit 0^e0 asserting IRQ1 does not
generate an SMI
3 1 21 SEE SYSTEM EVENT ENABLE REGISTER
Address Offset
Default Value
Attribute
Size
A4-A7h
00000000h
Read Write
32 Bits
For the 82374SB this register enables hardware events as system events or break events for power manage-
ment control Note that all of the functional bits in the SEE Register provide system event control In addition
all bits also provide break event control The default for each system break event in this register is disabled
System events Activity by these events can keep the system from powering down When a system event is
enabled the corresponding hardware event activity prevents a Fast Off powerdown condition Anytime the
corresponding hardware event occurs (signal is asserted) the Fast Off Timer is re-loaded with its initial count
Break events These events can awaken a powered down system When a break event is enabled the
corresponding hardware event activity powers up the system by negating STPCLK Note that STPCLK is
not negated until the stop grant special cycle has been generated by the CPU Thus from the time that
STPCLK is asserted until the stop grant cycle is returned the occurrence of subsequent break events are
latched in the ESC
NOTE
INIT is always enabled as a break event However INIT only causes a break event after a stop grant
special cycle has been received If INIT is asserted while STPCLK is active and then negated be-
fore the stop grant cycle is received INIT does not cause a break event
Bit
Description
31 Fast Off SMI Enable (FSMIEN) When bit 31^e1 (enabled) an SMI causes a system event that re-
loads the Fast Off Timer and a break event that negates the STPCLK signal When bit 31^e0
(disabled) an SMI does not re-load the Fast Off Timer or negate the STPCLK signal
30 Reserved
29 Fast Off NMI Enable (FNMIEN) When bit 29^e1 (enabled) an NMI (e g parity error) causes a system
event that re-loads the Fast Off Timer and a break event that negates the STPCLK signal When bit
29^e0 (disabled) an SMI does not re-load the Fast Off Timer or negate the STPCLK signal
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