82374EB Datasheet, PDF (28/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Pin Name Type
Description
EXTSMI
in EXTERNAL SYSTEM MANAGEMENT INTERRUPT EXTSMI is a falling edge
triggered input to the ESC indicating that an external device is requesting the system
to enter SMM mode When enabled via the SMI Enable Register a falling edge on
EXTSMI results in the assertion of the SMI signal to the CPU EXTSMI is an
asynchronous input to the ESC
INIT TEST in INITIALIZE TEST On the 82374SB the function of this pin is selected by the value
on the GPCS0 pin at reset If GPCS0 is low INIT is selected and if GPCS0 is
high TEST is selected On the 82374EB this pin only functions as the TEST pin
INIT
INIT is connected to the INIT pin on the CPU and indicates to the ESC that a CPU soft
reset is occuring When asserted the ESC ensures that STPCLK is negated when
the CPU comes out of the soft reset The ESC also blocks SMI generation when INIT
is asserted
TEST
For TEST signal description see the TEST signal section
STPGNT
in STPCLK GRANT When asserted STPGNT indicates to the ESC that a Stop grant
PCI special cycle was recognized by the PCEB The ESC may then negate the
STPCLK signal when the STPCLK Timer expires
2 10 ESC PCEB Interface Signals
2 10 1 ARBITRATION AND INTERRUPT ACKNOWLEDGE CONTROL
Pin Name Type
Description
EISAHOLD out EISA HOLD EISAHOLD is used to request control of the EISA bus from its default
owner the PCEB This signal is synchronous to PCICLK and is asserted when
RESET is asserted
EISAHLDA in EISA HOLD ACKNOWLEDGE EISAHLDA in used by the PCEB to inform the ESC
that it has been granted ownership of EISA bus This signal is synchronous to PCICLK
PEREQ
INTA
in PCI TO EISA REQUEST OR INTERRUPT ACKNOWLEDGE PEREQ INTA is a
dual function signal The context of the signal pin is determined by the state of
EISAHLDA signal
When EISAHLDA is deasserted this signal has the context of Interrupt Acknowledge
i e if PEREQ INTA is asserted it indicates to the ESC that current cycle on the
EISA is an interrupt acknowledge
When EISAHLDA is asserted this signal has the context of PCI-to-EISA Request i e if
PEREQ INTA is asserted it indicates to the ESC that PCEB needs to obtain the
ownership of the EISA bus on behalf of an PCI agent
This signal is synchronous to the PCICLK and it is driven inactive when RESET is
asserted
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