82374EB Datasheet, PDF (115/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Memory
Address
00h
01h
02h
10-2Fh
Table 8 I O APIC Registers
Mnemonic
Register Name
IOAPICID
IOAPICVER
IOAPICARB
IOREDTBL 0 15
I O APIC ID
I O APIC Version
I O APIC Arbitration ID
Redirection Table (Entries 0-15) (63 bits each)
NOTE
Address Offset is determined by I O Register Select Bits 7 0
Access
RW
RO
RO
RW
5 0 EISA CONTROLLER FUNCTIONAL DESCRIPTION
5 1 Overview
The EISA controller in the ESC provides Master Slave EISA interface function for the ESC internal resources
In addition the ESC acts as an EISA central resource for the system As a system central resource the EISA
controller is responsible for generating the translation control signals necessary for bus-to-bus transfers
These translation includes transfer between devices on EISA Bus and ISA Bus and transfers between different
size master device and slave device The EISA controller generates the control signals for EISA Data Swap
Buffers integrated in the PCEB The ESC EISA interface generates cycles for DMA transfers and refresh The
ESC internal registers are accessed through the EISA slave interface The ESC is responsible for supporting
the following
Service EISA Master cycles to
 EISA slaves devices
 ISA slave devices
 ESC internal registers
Service ISA Master cycles to
 EISA slave devices
 ISA (mis-matched) slave devices
 ESC internal registers
Service DMA cycles
 From to DMA slave on the EISA bus to from memory on the EISA ISA bus
 From to DMA slave on the ISA bus to from memory on the EISA ISA bus
 From to DMA slave on the EISA ISA bus to from memory on the PCI bus
Service Refresh Cycles
The EISA controller will service the refresh cycle by generating the appropriate address and command signals
These cycles are initiated by either the ESC internal refresh logic or by an external ISA-Bus Master
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