82374EB Datasheet, PDF (67/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Bit
Description
23 2 Upper Mid Lower Stop Bits These 22 bits provide the Stop Address If the Stop function is
enabled then the channel will Stop whenever its Memory Address matches the Stop Address
Bits 23 16 are the upper stop bits Bits 15 8 are the mid stop bits and bits 7 2 are the lower stop
bits Bits 1 0 are not used and are don’t cares
3 2 17 CHAIN CHAINING MODE REGISTER
Register Location
Default Value
Attribute
Size
040Ah Channels 0-3
04D4h Channels 4-7
000000xxb
Write Only
8 Bits
Each channel has a Chaining Mode register The Chaining Mode register enables or disables DMA buffer
chaining and indicates when the DMA Base registers are being programmed When writing to the register
bits 1 0 determine which channel’s Chaining Mode register to program The chaining status and interrupt
status for all channels can be determined by reading the Chaining Mode Status Channel Interrupt Status and
Chain Buffer Expiration Control registers The Chaining Mode register is reset to zero upon reset access (read
or write) of a channel’s Mode register or Extended Mode register or a Master Clear The values upon reset are
disable chaining mode and generate IRQ13
Bit
Description
7 5 Reserved Must be 0
4 Buffer Expired Signal After one of the two buffers in the DMA expires then the DMA will inform the
CPU that the next buffer should be loaded into the base register set This bit determines whether
IRQ13 or EOP should be used to inform the CPU that the buffer is complete 1^egenerate TC
0^eGenerate IRQ13 1^eProgramming complete 0^eDon’t start chaining
3 Base Register Programming After the reserve buffer’s address and word count are written to the
base register set this bit should be set to 1 to inform the DMA that the second buffer is ready for
transfer
2 Buffer Chaining Mode Bit 2 enables the chaining mode logic If the bit is set to 1 after the initial DMA
address and word count are programmed then the Base address and word count are available for
programming the next buffer in the chain 1^eEnable chaining 0^eDisable chaining
1 0 DMA Channel Select Bits 1 0 select the DMA channel mode register to program with bits 4 2
Bits 1 0
00
01
10
11
Channel
0 or 4
1 or 5
2 or 6
3 or 7
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