82374EB Datasheet, PDF (21/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Pin Name
MSBURST
MASTER16
SD 7 0
Type
Description
t s MASTER BURST MSBURST signal is asserted by an EISA master to indicate
EISA burst cycles MSBURST is asserted by an EISA master in response to an
asserted SLBURST signal The ESC samples SLBURST on the rising edge of
BCLK that CMD is asserted If asserted the ESC samples SLBURST on all
subsequent rising edges of BCLK until sampled negated The ESC keeps CMD
asserted during Burst cycles MSBURST is an output during DMA burst cycles
The ESC drives MSBURST active on the falling edge of BCLK one half BCLK
after SLBURST is sampled active at the end of START
in MASTER 16-BIT MASTER16 is asserted by a 16-bit EISA Bus master or an ISA
Bus master device to indicate that it has control of the EISA Bus or ISA Bus The
ESC samples MASTER16 on the rising edge of BCLK that START is asserted If
MASTER16 is sampled asserted the ESC determines that a 16-bit EISA Bus
master or an ISA Bus master owns the Bus If MASTER16 is sampled negated at
the first sampling point the ESC will sample MASTER16 a second time on the
rising edge of BCLK at the end of START If MASTER16 is sampled asserted
here the ESC determines that a 32-bit EISA Bus master has downshifted to a 16-bit
Bus master and thus the ESC will disable the data size translation function
t s SYSTEM DATA SD 7 0 signals are directly connected to the System Data bus
The SD 7 0 pins are outputs during I O reads when the ESC internal registers are
being accessed and during interrupt acknowledge cycles The SD 7 0 pins are
input during I O writes cycles when the ESC internal registers are being accessed
2 3 ISA Bus Signals
Pin Name Type
Description
BALE
out BUS ADDRESS LATCH ENABLE BALE signal is asserted by the ESC to indicate that
a address (SA 19 0 LA 23 17 ) AEN and SBHE signal lines are valid The
LA 23 17 address lines are latched on the trailing edge of BALE BALE remains active
throughout DMA and ISA Master cycles and Refresh cycles
SA 1 0
t s ISA ADDRESS BITS 0 1 SA 1 0 are the least significant bits of the ISA address bus
SA 1 0 are inputs to the ESC during ISA master cycles except during ISA master
initiated Refresh cycles The ESC uses the SA 1 0 in conjunction with SBHE to
generate BE 3 0 on the EISA bus The SA 1 0 are outputs of the ESC during EISA
master cycles and DMA cycles The ESC generates these from BE 3 0
SBHE
t s ISA BYTE HIGH ENABLE SBHE signal indicates that the high byte on the ISA data
bus (SD 15 8 ) is valid SBHE is an input to the ESC during ISA master cycles except
during ISA master initiated Refresh cycles The ESC uses the SBHE in conjunction
with SA 1 0 to generate BE 3 0 on the EISA bus SBHE is an output during EISA
master and DMA cycles
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