MC68HC908MR8 Datasheet, PDF (98/372 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
7.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
Because the MC68HC08MR8 has stop mode disabled by bit 1 in the
CONFIG register, execution of the STOP instruction will cause an illegal
opcode reset if stop mode has not been enabled by setting CONFIG
register bit 1.
7.4.2.4 Illegal Address Reset
An opcode fetch from addresses other than FLASH, I/O, or RAM
addresses generates an illegal address reset (unimplemented locations
within memory map). The SIM verifies that the CPU is fetching an
opcode prior to asserting the ILAD bit in the SIM reset status register
(SRSR) and resetting the MCU. A data fetch from an unmapped address
does not generate a reset.
7.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V_DD voltage falls to the LVI_LVRX voltage and remains at or below that
level for at least nine consecutive CPU cycles. The LVI bit in the SIM
reset status register (SRSR) is set, and the external reset pin (RST) is
held low while the SIM counter counts out 4096 CGMXCLK cycles.
Sixty-four CGMXCLK cycles later, the CPU is released from reset to
allow the reset vector sequence to occur. The SIM actively pulls down
the RST pin for all internal reset sources.
Technical Data
98
System Integration Module (SIM)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor