MC68HC908MR8 Datasheet, PDF (221/372 Pages) Motorola, Inc – Microcontrollers

Timer Interface A (TIMA)
I/O Registers
NOTE: Before enabling a TIMA channel register for input capture operation,
make sure that the PTBx/TACHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIMA counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIMA counter overflow.
0 = Channel x pin does not toggle on TIMA counter overflow.
NOTE: When TOVx is set, a TIMA counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100 percent. As
Figure 11-8 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100 percent duty cycle level
until the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
PERIOD
PTBx/TCHx
OVERFLOW
OVERFLOW
OVERFLOW
CHxMAX
TOVx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 11-8. CHxMAX Latency
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Timer Interface A (TIMA)
Technical Data
221