MC68HC908MR8 Datasheet, PDF (306/372 Pages) Motorola, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
17.4 Functional Description
Figure 17-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator.
The LVI power bit, LVIPWR, enables the LVI to monitor V_DD voltage. The
LVI reset bit, LVIRST, enables the LVI module to generate a reset when
V_DD falls below a voltage, V_LVRX, and remains at or below that level for
nine or more consecutive CGMXCLK.
• V_LVRX and V_LVHX are determined by the TRPSEL bit in the LVI
status and control register (LVISCR). See Figure 17-2.
• LVIPWR and LVIRST are in the configuration (CONFIG) register.
See 5.4 CONFIG Bits.
Once an LVI reset occurs, the MCU remains in reset until V_DD rises
above a voltage, V_LVRX + V_LVHX. V_DD must be above V_LVRX + V_LVHX for
only one central processor unit (CPU) cycle to bring the microcontroller
unit (MCU) out of reset. See 7.4.2.5 Low-Voltage Inhibit (LVI) Reset.
The output of the comparator controls the state of the LVIOUT flag in the
LVISCR.
NOTE: An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
V_DD
LOW V_DD
DETECTOR
LVIPWR
FROM CONFIG
CPU CLOCK
V_DD > LVITRIP = 0
V_DD < LVITRIP = 1
V_DD
DIGITAL FILTER
FROM CONFIG
LVIRST
TRPSEL
FROM LVISCR
ANLGTRIP
LVIOUT
Figure 17-1. LVI Module Block Diagram
LVI RESET
Technical Data
306
Low-Voltage Inhibit (LVI)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor